irqchip/versatile-fpga: Apply clear-mask earlier
commit5.4-rM2-2.2.x-imx-squashed6a214a2813
upstream. Clear its own IRQs before the parent IRQ get enabled, so that the remaining IRQs do not accidentally interrupt the parent IRQ controller. This patch also fixes a reboot bug on OX820 SoC, where the remaining rps-timer IRQ raises a GIC interrupt that is left pending. After that, the rps-timer IRQ is cleared during driver initialization, and there's no IRQ left in rps-irq when local_irq_enable() is called, which evokes an error message "unexpected IRQ trap". Fixes:bdd272cbb9
("irqchip: versatile FPGA: support cascaded interrupts from DT") Signed-off-by: Sungbo Eo <mans0n@gorani.run> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200321133842.2408823-1-mans0n@gorani.run Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
parent
3f3700c469
commit
6124e10dbc
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@ -212,6 +212,9 @@ int __init fpga_irq_of_init(struct device_node *node,
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if (of_property_read_u32(node, "valid-mask", &valid_mask))
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valid_mask = 0;
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writel(clear_mask, base + IRQ_ENABLE_CLEAR);
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writel(clear_mask, base + FIQ_ENABLE_CLEAR);
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/* Some chips are cascaded from a parent IRQ */
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parent_irq = irq_of_parse_and_map(node, 0);
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if (!parent_irq) {
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@ -221,9 +224,6 @@ int __init fpga_irq_of_init(struct device_node *node,
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fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
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writel(clear_mask, base + IRQ_ENABLE_CLEAR);
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writel(clear_mask, base + FIQ_ENABLE_CLEAR);
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/*
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* On Versatile AB/PB, some secondary interrupts have a direct
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* pass-thru to the primary controller for IRQs 20 and 22-31 which need
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