drm/amdgpu: use designated initializers
Prepare to mark sensitive kernel structures for randomization by making sure they're using designated initializers. These were identified during allyesconfig builds of x86, arm, and arm64, with most initializer fixes extracted from grsecurity. Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>hifive-unleashed-5.1
Kees Cook
Alex Deucher
parent
f7e9e9feb0
commit
613e61a025
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@ -1200,51 +1200,51 @@ static int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device,
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}
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static const struct cgs_ops amdgpu_cgs_ops = {
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amdgpu_cgs_gpu_mem_info,
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amdgpu_cgs_gmap_kmem,
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amdgpu_cgs_gunmap_kmem,
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amdgpu_cgs_alloc_gpu_mem,
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amdgpu_cgs_free_gpu_mem,
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amdgpu_cgs_gmap_gpu_mem,
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amdgpu_cgs_gunmap_gpu_mem,
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amdgpu_cgs_kmap_gpu_mem,
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amdgpu_cgs_kunmap_gpu_mem,
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amdgpu_cgs_read_register,
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amdgpu_cgs_write_register,
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amdgpu_cgs_read_ind_register,
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amdgpu_cgs_write_ind_register,
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amdgpu_cgs_read_pci_config_byte,
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amdgpu_cgs_read_pci_config_word,
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amdgpu_cgs_read_pci_config_dword,
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amdgpu_cgs_write_pci_config_byte,
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amdgpu_cgs_write_pci_config_word,
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amdgpu_cgs_write_pci_config_dword,
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amdgpu_cgs_get_pci_resource,
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amdgpu_cgs_atom_get_data_table,
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amdgpu_cgs_atom_get_cmd_table_revs,
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amdgpu_cgs_atom_exec_cmd_table,
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amdgpu_cgs_create_pm_request,
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amdgpu_cgs_destroy_pm_request,
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amdgpu_cgs_set_pm_request,
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amdgpu_cgs_pm_request_clock,
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amdgpu_cgs_pm_request_engine,
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amdgpu_cgs_pm_query_clock_limits,
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amdgpu_cgs_set_camera_voltages,
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amdgpu_cgs_get_firmware_info,
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amdgpu_cgs_rel_firmware,
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amdgpu_cgs_set_powergating_state,
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amdgpu_cgs_set_clockgating_state,
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amdgpu_cgs_get_active_displays_info,
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amdgpu_cgs_notify_dpm_enabled,
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amdgpu_cgs_call_acpi_method,
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amdgpu_cgs_query_system_info,
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amdgpu_cgs_is_virtualization_enabled
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.gpu_mem_info = amdgpu_cgs_gpu_mem_info,
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.gmap_kmem = amdgpu_cgs_gmap_kmem,
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.gunmap_kmem = amdgpu_cgs_gunmap_kmem,
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.alloc_gpu_mem = amdgpu_cgs_alloc_gpu_mem,
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.free_gpu_mem = amdgpu_cgs_free_gpu_mem,
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.gmap_gpu_mem = amdgpu_cgs_gmap_gpu_mem,
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.gunmap_gpu_mem = amdgpu_cgs_gunmap_gpu_mem,
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.kmap_gpu_mem = amdgpu_cgs_kmap_gpu_mem,
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.kunmap_gpu_mem = amdgpu_cgs_kunmap_gpu_mem,
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.read_register = amdgpu_cgs_read_register,
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.write_register = amdgpu_cgs_write_register,
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.read_ind_register = amdgpu_cgs_read_ind_register,
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.write_ind_register = amdgpu_cgs_write_ind_register,
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.read_pci_config_byte = amdgpu_cgs_read_pci_config_byte,
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.read_pci_config_word = amdgpu_cgs_read_pci_config_word,
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.read_pci_config_dword = amdgpu_cgs_read_pci_config_dword,
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.write_pci_config_byte = amdgpu_cgs_write_pci_config_byte,
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.write_pci_config_word = amdgpu_cgs_write_pci_config_word,
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.write_pci_config_dword = amdgpu_cgs_write_pci_config_dword,
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.get_pci_resource = amdgpu_cgs_get_pci_resource,
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.atom_get_data_table = amdgpu_cgs_atom_get_data_table,
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.atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs,
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.atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table,
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.create_pm_request = amdgpu_cgs_create_pm_request,
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.destroy_pm_request = amdgpu_cgs_destroy_pm_request,
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.set_pm_request = amdgpu_cgs_set_pm_request,
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.pm_request_clock = amdgpu_cgs_pm_request_clock,
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.pm_request_engine = amdgpu_cgs_pm_request_engine,
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.pm_query_clock_limits = amdgpu_cgs_pm_query_clock_limits,
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.set_camera_voltages = amdgpu_cgs_set_camera_voltages,
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.get_firmware_info = amdgpu_cgs_get_firmware_info,
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.rel_firmware = amdgpu_cgs_rel_firmware,
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.set_powergating_state = amdgpu_cgs_set_powergating_state,
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.set_clockgating_state = amdgpu_cgs_set_clockgating_state,
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.get_active_displays_info = amdgpu_cgs_get_active_displays_info,
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.notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled,
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.call_acpi_method = amdgpu_cgs_call_acpi_method,
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.query_system_info = amdgpu_cgs_query_system_info,
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.is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
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};
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static const struct cgs_os_ops amdgpu_cgs_os_ops = {
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amdgpu_cgs_add_irq_source,
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amdgpu_cgs_irq_get,
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amdgpu_cgs_irq_put
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.add_irq_source = amdgpu_cgs_add_irq_source,
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.irq_get = amdgpu_cgs_irq_get,
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.irq_put = amdgpu_cgs_irq_put
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};
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struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
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@ -243,9 +243,9 @@ static void amdgpu_gtt_mgr_debug(struct ttm_mem_type_manager *man,
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}
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const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func = {
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amdgpu_gtt_mgr_init,
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amdgpu_gtt_mgr_fini,
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amdgpu_gtt_mgr_new,
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amdgpu_gtt_mgr_del,
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amdgpu_gtt_mgr_debug
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.init = amdgpu_gtt_mgr_init,
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.takedown = amdgpu_gtt_mgr_fini,
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.get_node = amdgpu_gtt_mgr_new,
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.put_node = amdgpu_gtt_mgr_del,
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.debug = amdgpu_gtt_mgr_debug
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};
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@ -240,10 +240,16 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
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static const struct phm_master_table_item cz_enable_clock_power_gatings_list[] = {
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/*we don't need an exit table here, because there is only D3 cold on Kv*/
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{ phm_cf_want_uvd_power_gating, cz_tf_uvd_power_gating_initialize },
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{ phm_cf_want_vce_power_gating, cz_tf_vce_power_gating_initialize },
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{
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.isFunctionNeededInRuntimeTable = phm_cf_want_uvd_power_gating,
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.tableFunction = cz_tf_uvd_power_gating_initialize
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},
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{
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.isFunctionNeededInRuntimeTable = phm_cf_want_vce_power_gating,
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.tableFunction = cz_tf_vce_power_gating_initialize
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},
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/* to do { NULL, cz_tf_xdma_power_gating_enable }, */
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{ NULL, NULL }
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{ }
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};
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const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = {
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@ -888,13 +888,13 @@ static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
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}
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static const struct phm_master_table_item cz_set_power_state_list[] = {
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{NULL, cz_tf_update_sclk_limit},
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{NULL, cz_tf_set_deep_sleep_sclk_threshold},
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{NULL, cz_tf_set_watermark_threshold},
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{NULL, cz_tf_set_enabled_levels},
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{NULL, cz_tf_enable_nb_dpm},
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{NULL, cz_tf_update_low_mem_pstate},
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{NULL, NULL}
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{ .tableFunction = cz_tf_update_sclk_limit },
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{ .tableFunction = cz_tf_set_deep_sleep_sclk_threshold },
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{ .tableFunction = cz_tf_set_watermark_threshold },
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{ .tableFunction = cz_tf_set_enabled_levels },
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{ .tableFunction = cz_tf_enable_nb_dpm },
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{ .tableFunction = cz_tf_update_low_mem_pstate },
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{ }
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};
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static const struct phm_master_table_header cz_set_power_state_master = {
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@ -904,15 +904,15 @@ static const struct phm_master_table_header cz_set_power_state_master = {
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};
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static const struct phm_master_table_item cz_setup_asic_list[] = {
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{NULL, cz_tf_reset_active_process_mask},
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{NULL, cz_tf_upload_pptable_to_smu},
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{NULL, cz_tf_init_sclk_limit},
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{NULL, cz_tf_init_uvd_limit},
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{NULL, cz_tf_init_vce_limit},
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{NULL, cz_tf_init_acp_limit},
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{NULL, cz_tf_init_power_gate_state},
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{NULL, cz_tf_init_sclk_threshold},
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{NULL, NULL}
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{ .tableFunction = cz_tf_reset_active_process_mask },
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{ .tableFunction = cz_tf_upload_pptable_to_smu },
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{ .tableFunction = cz_tf_init_sclk_limit },
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{ .tableFunction = cz_tf_init_uvd_limit },
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{ .tableFunction = cz_tf_init_vce_limit },
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{ .tableFunction = cz_tf_init_acp_limit },
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{ .tableFunction = cz_tf_init_power_gate_state },
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{ .tableFunction = cz_tf_init_sclk_threshold },
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{ }
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};
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static const struct phm_master_table_header cz_setup_asic_master = {
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@ -957,10 +957,10 @@ static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
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}
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static const struct phm_master_table_item cz_power_down_asic_list[] = {
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{NULL, cz_tf_power_up_display_clock_sys_pll},
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{NULL, cz_tf_clear_nb_dpm_flag},
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{NULL, cz_tf_reset_cc6_data},
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{NULL, NULL}
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{ .tableFunction = cz_tf_power_up_display_clock_sys_pll },
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{ .tableFunction = cz_tf_clear_nb_dpm_flag },
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{ .tableFunction = cz_tf_reset_cc6_data },
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{ }
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};
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static const struct phm_master_table_header cz_power_down_asic_master = {
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@ -1068,8 +1068,8 @@ static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
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}
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static const struct phm_master_table_item cz_disable_dpm_list[] = {
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{ NULL, cz_tf_check_for_dpm_enabled},
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{NULL, NULL},
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{ .tableFunction = cz_tf_check_for_dpm_enabled },
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{ },
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};
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@ -1080,13 +1080,13 @@ static const struct phm_master_table_header cz_disable_dpm_master = {
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};
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static const struct phm_master_table_item cz_enable_dpm_list[] = {
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{ NULL, cz_tf_check_for_dpm_disabled },
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{ NULL, cz_tf_program_voting_clients },
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{ NULL, cz_tf_start_dpm},
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{ NULL, cz_tf_program_bootup_state},
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{ NULL, cz_tf_enable_didt },
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{ NULL, cz_tf_reset_acp_boot_level },
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{NULL, NULL},
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{ .tableFunction = cz_tf_check_for_dpm_disabled },
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{ .tableFunction = cz_tf_program_voting_clients },
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{ .tableFunction = cz_tf_start_dpm },
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{ .tableFunction = cz_tf_program_bootup_state },
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{ .tableFunction = cz_tf_enable_didt },
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{ .tableFunction = cz_tf_reset_acp_boot_level },
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{ },
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};
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static const struct phm_master_table_header cz_enable_dpm_master = {
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@ -506,18 +506,18 @@ static int tf_smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr,
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static const struct phm_master_table_item
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phm_thermal_start_thermal_controller_master_list[] = {
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{NULL, tf_smu7_thermal_initialize},
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{NULL, tf_smu7_thermal_set_temperature_range},
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{NULL, tf_smu7_thermal_enable_alert},
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{NULL, smum_thermal_avfs_enable},
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{ .tableFunction = tf_smu7_thermal_initialize },
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{ .tableFunction = tf_smu7_thermal_set_temperature_range },
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{ .tableFunction = tf_smu7_thermal_enable_alert },
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{ .tableFunction = smum_thermal_avfs_enable },
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/* We should restrict performance levels to low before we halt the SMC.
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* On the other hand we are still in boot state when we do this
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* so it would be pointless.
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* If this assumption changes we have to revisit this table.
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*/
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{NULL, smum_thermal_setup_fan_table},
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{NULL, tf_smu7_thermal_start_smc_fan_control},
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{NULL, NULL}
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{ .tableFunction = smum_thermal_setup_fan_table },
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{ .tableFunction = tf_smu7_thermal_start_smc_fan_control },
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{ }
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};
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static const struct phm_master_table_header
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@ -529,10 +529,10 @@ phm_thermal_start_thermal_controller_master = {
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static const struct phm_master_table_item
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phm_thermal_set_temperature_range_master_list[] = {
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{NULL, tf_smu7_thermal_disable_alert},
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{NULL, tf_smu7_thermal_set_temperature_range},
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{NULL, tf_smu7_thermal_enable_alert},
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{NULL, NULL}
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{ .tableFunction = tf_smu7_thermal_disable_alert },
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{ .tableFunction = tf_smu7_thermal_set_temperature_range },
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{ .tableFunction = tf_smu7_thermal_enable_alert },
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{ }
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};
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static const struct phm_master_table_header
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