arm64: Atomic operations
This patch introduces the atomic, mutex and futex operations. Many atomic operations use the load-acquire and store-release operations which imply barriers, avoiding the need for explicit DMB. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
Catalin Marinas
parent
fb9bd7d6df
commit
6170a97460
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/*
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* Based on arch/arm/include/asm/atomic.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2002 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ATOMIC_H
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#define __ASM_ATOMIC_H
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/barrier.h>
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#include <asm/cmpxchg.h>
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#define ATOMIC_INIT(i) { (i) }
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#ifdef __KERNEL__
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/*
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* On ARM, ordinary assignment (str instruction) doesn't clear the local
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* strex/ldrex monitor on some implementations. The reason we can use it for
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* atomic_set() is the clrex or dummy strex done on every exception return.
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*/
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#define atomic_read(v) (*(volatile int *)&(v)->counter)
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#define atomic_set(v,i) (((v)->counter) = (i))
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/*
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* AArch64 UP and SMP safe atomic ops. We use load exclusive and
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* store exclusive to ensure that these are atomic. We may loop
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* to ensure that the update happens.
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*/
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static inline void atomic_add(int i, atomic_t *v)
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{
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unsigned long tmp;
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int result;
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asm volatile("// atomic_add\n"
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"1: ldxr %w0, [%3]\n"
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" add %w0, %w0, %w4\n"
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" stxr %w1, %w0, [%3]\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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}
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long tmp;
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int result;
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asm volatile("// atomic_add_return\n"
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"1: ldaxr %w0, [%3]\n"
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" add %w0, %w0, %w4\n"
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" stlxr %w1, %w0, [%3]\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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return result;
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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unsigned long tmp;
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int result;
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asm volatile("// atomic_sub\n"
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"1: ldxr %w0, [%3]\n"
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" sub %w0, %w0, %w4\n"
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" stxr %w1, %w0, [%3]\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned long tmp;
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int result;
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asm volatile("// atomic_sub_return\n"
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"1: ldaxr %w0, [%3]\n"
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" sub %w0, %w0, %w4\n"
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" stlxr %w1, %w0, [%3]\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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return result;
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}
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static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
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{
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unsigned long tmp;
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int oldval;
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asm volatile("// atomic_cmpxchg\n"
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"1: ldaxr %w1, [%3]\n"
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" cmp %w1, %w4\n"
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" b.ne 2f\n"
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" stlxr %w0, %w5, [%3]\n"
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" cbnz %w0, 1b\n"
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"2:"
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: "=&r" (tmp), "=&r" (oldval), "+o" (ptr->counter)
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: "r" (&ptr->counter), "Ir" (old), "r" (new)
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: "cc");
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return oldval;
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}
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static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
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{
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unsigned long tmp, tmp2;
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asm volatile("// atomic_clear_mask\n"
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"1: ldxr %0, [%3]\n"
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" bic %0, %0, %4\n"
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" stxr %w1, %0, [%3]\n"
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" cbnz %w1, 1b"
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: "=&r" (tmp), "=&r" (tmp2), "+o" (*addr)
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: "r" (addr), "Ir" (mask)
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: "cc");
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}
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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static inline int __atomic_add_unless(atomic_t *v, int a, int u)
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{
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int c, old;
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c = atomic_read(v);
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while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
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c = old;
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return c;
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}
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#define atomic_inc(v) atomic_add(1, v)
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#define atomic_dec(v) atomic_sub(1, v)
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#define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
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#define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
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#define atomic_inc_return(v) (atomic_add_return(1, v))
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#define atomic_dec_return(v) (atomic_sub_return(1, v))
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#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
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#define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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/*
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* 64-bit atomic operations.
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*/
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#define ATOMIC64_INIT(i) { (i) }
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#define atomic64_read(v) (*(volatile long long *)&(v)->counter)
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#define atomic64_set(v,i) (((v)->counter) = (i))
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static inline void atomic64_add(u64 i, atomic64_t *v)
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{
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long result;
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unsigned long tmp;
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asm volatile("// atomic64_add\n"
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"1: ldxr %0, [%3]\n"
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" add %0, %0, %4\n"
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" stxr %w1, %0, [%3]\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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}
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static inline long atomic64_add_return(long i, atomic64_t *v)
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{
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long result;
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unsigned long tmp;
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asm volatile("// atomic64_add_return\n"
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"1: ldaxr %0, [%3]\n"
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" add %0, %0, %4\n"
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" stlxr %w1, %0, [%3]\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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return result;
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}
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static inline void atomic64_sub(u64 i, atomic64_t *v)
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{
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long result;
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unsigned long tmp;
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asm volatile("// atomic64_sub\n"
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"1: ldxr %0, [%3]\n"
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" sub %0, %0, %4\n"
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" stxr %w1, %0, [%3]\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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}
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static inline long atomic64_sub_return(long i, atomic64_t *v)
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{
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long result;
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unsigned long tmp;
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asm volatile("// atomic64_sub_return\n"
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"1: ldaxr %0, [%3]\n"
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" sub %0, %0, %4\n"
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" stlxr %w1, %0, [%3]\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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return result;
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}
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static inline long atomic64_cmpxchg(atomic64_t *ptr, long old, long new)
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{
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long oldval;
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unsigned long res;
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asm volatile("// atomic64_cmpxchg\n"
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"1: ldaxr %1, [%3]\n"
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" cmp %1, %4\n"
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" b.ne 2f\n"
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" stlxr %w0, %5, [%3]\n"
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" cbnz %w0, 1b\n"
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"2:"
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: "=&r" (res), "=&r" (oldval), "+o" (ptr->counter)
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: "r" (&ptr->counter), "Ir" (old), "r" (new)
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: "cc");
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return oldval;
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}
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#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
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static inline long atomic64_dec_if_positive(atomic64_t *v)
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{
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long result;
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unsigned long tmp;
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asm volatile("// atomic64_dec_if_positive\n"
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"1: ldaxr %0, [%3]\n"
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" subs %0, %0, #1\n"
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" b.mi 2f\n"
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" stlxr %w1, %0, [%3]\n"
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" cbnz %w1, 1b\n"
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"2:"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter)
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: "cc");
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return result;
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}
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static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
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{
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long c, old;
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c = atomic64_read(v);
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while (c != u && (old = atomic64_cmpxchg((v), c, c + a)) != c)
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c = old;
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return c != u;
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}
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#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
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#define atomic64_inc(v) atomic64_add(1LL, (v))
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#define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
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#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
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#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
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#define atomic64_dec(v) atomic64_sub(1LL, (v))
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#define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
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#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
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#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
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#endif
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#endif
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@ -0,0 +1,136 @@
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/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_FUTEX_H
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#define __ASM_FUTEX_H
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#ifdef __KERNEL__
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/errno.h>
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#define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \
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asm volatile( \
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"1: ldaxr %w1, %2\n" \
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insn "\n" \
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"2: stlxr %w3, %w0, %2\n" \
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" cbnz %w3, 1b\n" \
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"3:\n" \
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" .pushsection .fixup,\"ax\"\n" \
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"4: mov %w0, %w5\n" \
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" b 3b\n" \
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" .popsection\n" \
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" .pushsection __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .quad 1b, 4b, 2b, 4b\n" \
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" .popsection\n" \
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: "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \
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: "r" (oparg), "Ir" (-EFAULT) \
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: "cc")
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static inline int
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futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
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{
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int op = (encoded_op >> 28) & 7;
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int cmp = (encoded_op >> 24) & 15;
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int oparg = (encoded_op << 8) >> 20;
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int cmparg = (encoded_op << 20) >> 20;
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int oldval = 0, ret, tmp;
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if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
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oparg = 1 << oparg;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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return -EFAULT;
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pagefault_disable(); /* implies preempt_disable() */
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("mov %w0, %w4",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("add %w0, %w1, %w4",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("orr %w0, %w1, %w4",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("and %w0, %w1, %w4",
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ret, oldval, uaddr, tmp, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("eor %w0, %w1, %w4",
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ret, oldval, uaddr, tmp, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable(); /* subsumes preempt_enable() */
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if (!ret) {
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switch (cmp) {
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case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
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case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
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case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
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case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
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case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
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case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
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default: ret = -ENOSYS;
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}
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}
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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u32 oldval, u32 newval)
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{
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int ret = 0;
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u32 val, tmp;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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return -EFAULT;
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asm volatile("// futex_atomic_cmpxchg_inatomic\n"
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"1: ldaxr %w1, %2\n"
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" sub %w3, %w1, %w4\n"
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" cbnz %w3, 3f\n"
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"2: stlxr %w3, %w5, %2\n"
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" cbnz %w3, 1b\n"
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"3:\n"
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" .pushsection .fixup,\"ax\"\n"
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"4: mov %w0, %w6\n"
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" b 3b\n"
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" .popsection\n"
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" .pushsection __ex_table,\"a\"\n"
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" .align 3\n"
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" .quad 1b, 4b, 2b, 4b\n"
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" .popsection\n"
|
||||
: "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp)
|
||||
: "r" (oldval), "r" (newval), "Ir" (-EFAULT)
|
||||
: "cc", "memory");
|
||||
|
||||
*uval = val;
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* __ASM_FUTEX_H */
|
||||
Loading…
Reference in New Issue