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drm/tegra: sor: Use sor1_src clock to set parent for HDMI 

When running in HDMI mode, the sor1 IP block needs to use the sor1_src
as parent clock, and in turn configure the sor1_src to use pll_d2_out0
as its parent.

Signed-off-by: Thierry Reding <treding@nvidia.com>
hifive-unleashed-5.1
Thierry Reding 2016-06-09 17:53:57 +02:00
parent 5d2304c1de
commit 618dee3941
1 changed files with 16 additions and 1 deletions
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17
drivers/gpu/drm/tegra/sor.c
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@ -173,6 +173,7 @@ struct tegra_sor {
struct clk *clk_parent;
struct clk *clk_brick;
struct clk *clk_safe;
struct clk *clk_src;
struct clk *clk_dp;
struct clk *clk;
@ -2101,7 +2102,11 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
/* switch to parent clock */
err = tegra_sor_set_parent_clock(sor, sor->clk_parent);
err = clk_set_parent(sor->clk_src, sor->clk_parent);
if (err < 0)
dev_err(sor->dev, "failed to set source clock: %d\n", err);
err = tegra_sor_set_parent_clock(sor, sor->clk_src);
if (err < 0)
dev_err(sor->dev, "failed to set parent clock: %d\n", err);
@ -2595,6 +2600,16 @@ static int tegra_sor_probe(struct platform_device *pdev)
goto remove;
}
if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
sor->clk_src = devm_clk_get(&pdev->dev, "source");
if (IS_ERR(sor->clk_src)) {
err = PTR_ERR(sor->clk_src);
dev_err(sor->dev, "failed to get source clock: %d\n",
err);
goto remove;
}
}
sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
if (IS_ERR(sor->clk_parent)) {
err = PTR_ERR(sor->clk_parent);