[SPARC64]: Hypervisor TSB context switching.
Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
David S. Miller
parent
aa9143b971
commit
618e9ed98a
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@ -4,6 +4,7 @@
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*/
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#include <asm/tsb.h>
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#include <asm/hypervisor.h>
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.text
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.align 32
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@ -233,6 +234,7 @@ tsb_flush:
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* %o1: TSB register value
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* %o2: TSB virtual address
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* %o3: TSB mapping locked PTE
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* %o4: Hypervisor TSB descriptor physical address
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*
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* We have to run this whole thing with interrupts
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* disabled so that the current cpu doesn't change
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@ -251,30 +253,40 @@ __tsb_context_switch:
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add %g2, %g1, %g2
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stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
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661: mov TSB_REG, %g1
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stxa %o1, [%g1] ASI_DMMU
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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mov SCRATCHPAD_UTSBREG1, %g1
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stxa %o1, [%g1] ASI_SCRATCHPAD
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.previous
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membar #Sync
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661: stxa %o1, [%g1] ASI_IMMU
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membar #Sync
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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brz %o2, 9f
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sethi %hi(tlb_type), %g1
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lduw [%g1 + %lo(tlb_type)], %g1
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cmp %g1, 3
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bne,pt %icc, 1f
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nop
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sethi %hi(sparc64_highest_unlocked_tlb_ent), %o4
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/* Hypervisor TSB switch. */
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mov SCRATCHPAD_UTSBREG1, %g1
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stxa %o1, [%g1] ASI_SCRATCHPAD
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mov -1, %g2
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mov SCRATCHPAD_UTSBREG2, %g1
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stxa %g2, [%g1] ASI_SCRATCHPAD
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mov HV_FAST_MMU_TSB_CTXNON0, %o0
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mov 1, %o1
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mov %o4, %o2
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ta HV_FAST_TRAP
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ba,pt %xcc, 9f
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nop
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/* SUN4U TSB switch. */
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1: mov TSB_REG, %g1
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stxa %o1, [%g1] ASI_DMMU
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membar #Sync
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stxa %o1, [%g1] ASI_IMMU
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membar #Sync
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2: brz %o2, 9f
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nop
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sethi %hi(sparc64_highest_unlocked_tlb_ent), %g2
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mov TLB_TAG_ACCESS, %g1
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lduw [%o4 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
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lduw [%g2 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
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stxa %o2, [%g1] ASI_DMMU
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membar #Sync
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sllx %g2, 3, %g2
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@ -149,7 +149,7 @@ static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_bytes)
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BUG();
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};
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if (tlb_type == cheetah_plus) {
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if (tlb_type == cheetah_plus || tlb_type == hypervisor) {
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/* Physical mapping, no locked TLB entry for TSB. */
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tsb_reg |= tsb_paddr;
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@ -166,6 +166,52 @@ static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_bytes)
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mm->context.tsb_map_pte = tte;
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}
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/* Setup the Hypervisor TSB descriptor. */
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if (tlb_type == hypervisor) {
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struct hv_tsb_descr *hp = &mm->context.tsb_descr;
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switch (PAGE_SIZE) {
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case 8192:
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default:
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hp->pgsz_idx = HV_PGSZ_IDX_8K;
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break;
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case 64 * 1024:
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hp->pgsz_idx = HV_PGSZ_IDX_64K;
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break;
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case 512 * 1024:
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hp->pgsz_idx = HV_PGSZ_IDX_512K;
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break;
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case 4 * 1024 * 1024:
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hp->pgsz_idx = HV_PGSZ_IDX_4MB;
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break;
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};
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hp->assoc = 1;
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hp->num_ttes = tsb_bytes / 16;
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hp->ctx_idx = 0;
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switch (PAGE_SIZE) {
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case 8192:
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default:
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hp->pgsz_mask = HV_PGSZ_MASK_8K;
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break;
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case 64 * 1024:
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hp->pgsz_mask = HV_PGSZ_MASK_64K;
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break;
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case 512 * 1024:
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hp->pgsz_mask = HV_PGSZ_MASK_512K;
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break;
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case 4 * 1024 * 1024:
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hp->pgsz_mask = HV_PGSZ_MASK_4MB;
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break;
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};
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hp->tsb_base = tsb_paddr;
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hp->resv = 0;
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}
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}
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/* The page tables are locked against modifications while this
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@ -4,6 +4,7 @@
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#include <linux/config.h>
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#include <asm/page.h>
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#include <asm/const.h>
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#include <asm/hypervisor.h>
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/*
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* For the 8k pagesize kernel, use only 10 hw context bits to optimize some
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@ -101,13 +102,14 @@ extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte
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extern void tsb_flush(unsigned long ent, unsigned long tag);
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typedef struct {
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unsigned long sparc64_ctx_val;
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struct tsb *tsb;
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unsigned long tsb_rss_limit;
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unsigned long tsb_nentries;
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unsigned long tsb_reg_val;
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unsigned long tsb_map_vaddr;
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unsigned long tsb_map_pte;
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unsigned long sparc64_ctx_val;
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struct tsb *tsb;
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unsigned long tsb_rss_limit;
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unsigned long tsb_nentries;
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unsigned long tsb_reg_val;
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unsigned long tsb_map_vaddr;
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unsigned long tsb_map_pte;
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struct hv_tsb_descr tsb_descr;
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} mm_context_t;
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#endif /* !__ASSEMBLY__ */
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@ -22,14 +22,18 @@ extern void get_new_mmu_context(struct mm_struct *mm);
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extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
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extern void destroy_context(struct mm_struct *mm);
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extern void __tsb_context_switch(unsigned long pgd_pa, unsigned long tsb_reg,
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unsigned long tsb_vaddr, unsigned long tsb_pte);
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extern void __tsb_context_switch(unsigned long pgd_pa,
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unsigned long tsb_reg,
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unsigned long tsb_vaddr,
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unsigned long tsb_pte,
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unsigned long tsb_descr_pa);
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static inline void tsb_context_switch(struct mm_struct *mm)
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{
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__tsb_context_switch(__pa(mm->pgd), mm->context.tsb_reg_val,
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mm->context.tsb_map_vaddr,
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mm->context.tsb_map_pte);
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mm->context.tsb_map_pte,
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__pa(&mm->context.tsb_descr));
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}
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extern void tsb_grow(struct mm_struct *mm, unsigned long mm_rss, gfp_t gfp_flags);
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