drm/i915: Abstract PPGTT enabling
Since we've already set up a nice vtable to abstract other PPGTT functions, also abstract the actual register programming to enable things. This function will probably need to change a bit as we implement real processes. v2: Resolve conflicts due to patch series reordering. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -927,7 +927,8 @@ int i915_reset(struct drm_device *dev)
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ring->init(ring);
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ring->init(ring);
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i915_gem_context_init(dev);
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i915_gem_context_init(dev);
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i915_gem_init_ppgtt(dev);
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if (dev_priv->mm.aliasing_ppgtt)
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dev_priv->mm.aliasing_ppgtt->enable(dev);
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/*
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/*
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* It would make sense to re-init all the other hw state, at
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* It would make sense to re-init all the other hw state, at
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@ -449,6 +449,7 @@ struct i915_hw_ppgtt {
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struct sg_table *st,
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struct sg_table *st,
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unsigned int pg_start,
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unsigned int pg_start,
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enum i915_cache_level cache_level);
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enum i915_cache_level cache_level);
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void (*enable)(struct drm_device *dev);
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void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
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void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
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};
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};
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@ -1642,7 +1643,6 @@ int __must_check i915_gem_init(struct drm_device *dev);
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int __must_check i915_gem_init_hw(struct drm_device *dev);
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int __must_check i915_gem_init_hw(struct drm_device *dev);
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void i915_gem_l3_remap(struct drm_device *dev);
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void i915_gem_l3_remap(struct drm_device *dev);
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void i915_gem_init_swizzling(struct drm_device *dev);
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void i915_gem_init_swizzling(struct drm_device *dev);
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void i915_gem_init_ppgtt(struct drm_device *dev);
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void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
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void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
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int __must_check i915_gpu_idle(struct drm_device *dev);
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int __must_check i915_gpu_idle(struct drm_device *dev);
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int __must_check i915_gem_idle(struct drm_device *dev);
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int __must_check i915_gem_idle(struct drm_device *dev);
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@ -4029,7 +4029,8 @@ i915_gem_init_hw(struct drm_device *dev)
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* contexts before PPGTT.
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* contexts before PPGTT.
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*/
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*/
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i915_gem_context_init(dev);
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i915_gem_context_init(dev);
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i915_gem_init_ppgtt(dev);
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if (dev_priv->mm.aliasing_ppgtt)
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dev_priv->mm.aliasing_ppgtt->enable(dev);
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return 0;
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return 0;
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}
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}
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@ -75,6 +75,61 @@ static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
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return pte;
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return pte;
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}
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}
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static void gen6_ppgtt_enable(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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uint32_t pd_offset;
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struct intel_ring_buffer *ring;
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struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
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gen6_gtt_pte_t __iomem *pd_addr;
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uint32_t pd_entry;
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int i;
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pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
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ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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dma_addr_t pt_addr;
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pt_addr = ppgtt->pt_dma_addr[i];
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pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
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pd_entry |= GEN6_PDE_VALID;
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writel(pd_entry, pd_addr + i);
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}
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readl(pd_addr);
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pd_offset = ppgtt->pd_offset;
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pd_offset /= 64; /* in cachelines, */
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pd_offset <<= 16;
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if (INTEL_INFO(dev)->gen == 6) {
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uint32_t ecochk, gab_ctl, ecobits;
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ecobits = I915_READ(GAC_ECO_BITS);
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I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
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gab_ctl = I915_READ(GAB_CTL);
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I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
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ecochk = I915_READ(GAM_ECOCHK);
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I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
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ECOCHK_PPGTT_CACHE64B);
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I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
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} else if (INTEL_INFO(dev)->gen >= 7) {
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I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
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/* GFX_MODE is per-ring on gen7+ */
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}
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for_each_ring(ring, dev_priv, i) {
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if (INTEL_INFO(dev)->gen >= 7)
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I915_WRITE(RING_MODE_GEN7(ring),
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_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
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I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
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I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
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}
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}
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/* PPGTT support for Sandybdrige/Gen6 and later */
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/* PPGTT support for Sandybdrige/Gen6 and later */
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static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
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static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
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unsigned first_entry,
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unsigned first_entry,
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@ -168,6 +223,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
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gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
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gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
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ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
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ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
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ppgtt->enable = gen6_ppgtt_enable;
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ppgtt->clear_range = gen6_ppgtt_clear_range;
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ppgtt->clear_range = gen6_ppgtt_clear_range;
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ppgtt->insert_entries = gen6_ppgtt_insert_entries;
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ppgtt->insert_entries = gen6_ppgtt_insert_entries;
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ppgtt->cleanup = gen6_ppgtt_cleanup;
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ppgtt->cleanup = gen6_ppgtt_cleanup;
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@ -279,64 +335,6 @@ void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
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obj->base.size >> PAGE_SHIFT);
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obj->base.size >> PAGE_SHIFT);
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}
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}
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void i915_gem_init_ppgtt(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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uint32_t pd_offset;
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struct intel_ring_buffer *ring;
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struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
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gen6_gtt_pte_t __iomem *pd_addr;
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uint32_t pd_entry;
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int i;
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if (!dev_priv->mm.aliasing_ppgtt)
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return;
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pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
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ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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dma_addr_t pt_addr;
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pt_addr = ppgtt->pt_dma_addr[i];
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pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
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pd_entry |= GEN6_PDE_VALID;
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writel(pd_entry, pd_addr + i);
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}
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readl(pd_addr);
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pd_offset = ppgtt->pd_offset;
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pd_offset /= 64; /* in cachelines, */
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pd_offset <<= 16;
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if (INTEL_INFO(dev)->gen == 6) {
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uint32_t ecochk, gab_ctl, ecobits;
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ecobits = I915_READ(GAC_ECO_BITS);
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I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
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gab_ctl = I915_READ(GAB_CTL);
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I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
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ecochk = I915_READ(GAM_ECOCHK);
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I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
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ECOCHK_PPGTT_CACHE64B);
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I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
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} else if (INTEL_INFO(dev)->gen >= 7) {
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I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
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/* GFX_MODE is per-ring on gen7+ */
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}
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for_each_ring(ring, dev_priv, i) {
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if (INTEL_INFO(dev)->gen >= 7)
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I915_WRITE(RING_MODE_GEN7(ring),
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_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
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I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
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I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
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}
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}
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extern int intel_iommu_gfx_mapped;
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extern int intel_iommu_gfx_mapped;
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/* Certain Gen5 chipsets require require idling the GPU before
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/* Certain Gen5 chipsets require require idling the GPU before
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* unmapping anything from the GTT when VT-d is enabled.
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* unmapping anything from the GTT when VT-d is enabled.
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