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drm/meson: Switch PLL to 5.94GHz base for 297Mhz pixel clock 

On Amlogic G12A SoC, the 2,97GHz PLL frequency is not stable enough
to provide a correct 297MHz pixel clock, so switch the PLL base
frequency with a /2 OD when the 297MHz pixel clock is requested.

This solves the issue on G12A and also works fine on GXBB, GXL & GXM.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-2-narmstrong@baylibre.com
hifive-unleashed-5.2
Neil Armstrong 2019-03-25 15:18:14 +01:00
parent 6c28dca669
commit 61af6e22ec
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/meson/meson_vclk.c
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@ -396,8 +396,8 @@ struct meson_vclk_params {
},
[MESON_VCLK_HDMI_297000] = {
.pixel_freq = 297000,
.pll_base_freq = 2970000,
.pll_od1 = 1,
.pll_base_freq = 5940000,
.pll_od1 = 2,
.pll_od2 = 1,
.pll_od3 = 1,
.vid_pll_div = VID_PLL_DIV_5,