redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

ARM: integrator: Convert PCI to use generic config accessors 

Convert the integrator PCI driver to use the generic config access
functions.

This changes accesses from __raw_readX/__raw_writeX to readX/writeX
variants.  The spinlock is removed because it is unnecessary.  The config
read and write functions are already protected with a spinlock and no
access can occur during the .pre_init function.

[arnd: remove unused "flags"]
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
CC: Russell King <linux@arm.linux.org.uk>
CC: linux-arm-kernel@lists.infradead.org
hifive-unleashed-5.1
Rob Herring 2015-01-09 20:34:41 -06:00 committed by Bjorn Helgaas
parent 802b7c06ad
commit 61dc485b90
1 changed files with 5 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

62
arch/arm/mach-integrator/pci_v3.c
View File

@ -356,7 +356,6 @@ static u64 pre_mem_pci_sz;
* 7:2 register number
*
*/
static DEFINE_RAW_SPINLOCK(v3_lock);
#undef V3_LB_BASE_PREFETCH
#define V3_LB_BASE_PREFETCH 0
@ -457,67 +456,21 @@ static void v3_close_config_window(void)
static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 *val)
{
void __iomem *addr;
unsigned long flags;
u32 v;
raw_spin_lock_irqsave(&v3_lock, flags);
addr = v3_open_config_window(bus, devfn, where);
switch (size) {
case 1:
v = __raw_readb(addr);
break;
case 2:
v = __raw_readw(addr);
break;
default:
v = __raw_readl(addr);
break;
}
int ret = pci_generic_config_read(bus, devfn, where, size, val);
v3_close_config_window();
raw_spin_unlock_irqrestore(&v3_lock, flags);
*val = v;
return PCIBIOS_SUCCESSFUL;
return ret;
}
static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 val)
{
void __iomem *addr;
unsigned long flags;
raw_spin_lock_irqsave(&v3_lock, flags);
addr = v3_open_config_window(bus, devfn, where);
switch (size) {
case 1:
__raw_writeb((u8)val, addr);
__raw_readb(addr);
break;
case 2:
__raw_writew((u16)val, addr);
__raw_readw(addr);
break;
case 4:
__raw_writel(val, addr);
__raw_readl(addr);
break;
}
int ret = pci_generic_config_write(bus, devfn, where, size, val);
v3_close_config_window();
raw_spin_unlock_irqrestore(&v3_lock, flags);
return PCIBIOS_SUCCESSFUL;
return ret;
}
static struct pci_ops pci_v3_ops = {
.map_bus = v3_open_config_window,
.read = v3_read_config,
.write = v3_write_config,
};
@ -658,7 +611,6 @@ static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
*/
static void __init pci_v3_preinit(void)
{
unsigned long flags;
unsigned int temp;
phys_addr_t io_address = pci_pio_to_address(io_mem.start);
@ -672,8 +624,6 @@ static void __init pci_v3_preinit(void)
hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
raw_spin_lock_irqsave(&v3_lock, flags);
/*
* Unlock V3 registers, but only if they were previously locked.
*/
@ -736,8 +686,6 @@ static void __init pci_v3_preinit(void)
v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
v3_writeb(V3_LB_IMASK, 0x28);
__raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
raw_spin_unlock_irqrestore(&v3_lock, flags);
}
static void __init pci_v3_postinit(void)