drm/i915: Simplify enabling user-interrupts with L3-remapping
Borrow the idea from intel_lrc.c to precompute the mask of interrupts we wish to always enable to avoid having lots of conditionals inside the interrupt enabling. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-19-git-send-email-chris@chris-wilson.co.uk
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@ -1313,8 +1313,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
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if (IS_GEN(dev_priv, 6, 7))
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I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
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if (HAS_L3_DPF(dev_priv))
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I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
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I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
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return init_workarounds_ring(engine);
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}
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@ -1729,12 +1728,9 @@ gen6_irq_enable(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
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I915_WRITE_IMR(engine,
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~(engine->irq_enable_mask |
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GT_PARITY_ERROR(dev_priv)));
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else
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I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
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I915_WRITE_IMR(engine,
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~(engine->irq_enable_mask |
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engine->irq_keep_mask));
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gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
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}
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@ -1743,10 +1739,7 @@ gen6_irq_disable(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
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I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
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else
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I915_WRITE_IMR(engine, ~0);
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I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
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gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
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}
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@ -1773,12 +1766,9 @@ gen8_irq_enable(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
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I915_WRITE_IMR(engine,
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~(engine->irq_enable_mask |
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GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
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else
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I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
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I915_WRITE_IMR(engine,
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~(engine->irq_enable_mask |
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engine->irq_keep_mask));
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POSTING_READ_FW(RING_IMR(engine->mmio_base));
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}
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@ -1787,11 +1777,7 @@ gen8_irq_disable(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
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I915_WRITE_IMR(engine,
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~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
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else
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I915_WRITE_IMR(engine, ~0);
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I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
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}
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static int
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@ -2872,6 +2858,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
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intel_ring_default_vfuncs(dev_priv, engine);
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engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
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if (HAS_L3_DPF(dev_priv))
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engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
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if (INTEL_GEN(dev_priv) >= 8) {
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engine->init_context = intel_rcs_ctx_init;
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@ -190,7 +190,8 @@ struct intel_engine_cs {
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struct i915_ctx_workarounds wa_ctx;
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bool irq_posted;
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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u32 irq_keep_mask; /* always keep these interrupts */
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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void (*irq_enable)(struct intel_engine_cs *ring);
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void (*irq_disable)(struct intel_engine_cs *ring);
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@ -287,7 +288,6 @@ struct intel_engine_cs {
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unsigned int idle_lite_restore_wa;
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bool disable_lite_restore_wa;
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u32 ctx_desc_template;
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u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
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int (*emit_request)(struct drm_i915_gem_request *request);
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int (*emit_flush)(struct drm_i915_gem_request *request,
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u32 invalidate_domains,
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