ARM: SAMSUNG: Add support s3c2443-adc for S3C2443
The S3C2443-adc is 10 bit wide and has its mux-select in an extra register at base+0x18 Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -41,6 +41,7 @@
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#include <plat/cpu.h>
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#include <plat/cpu.h>
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#include <plat/fb-core.h>
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#include <plat/fb-core.h>
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#include <plat/nand-core.h>
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#include <plat/nand-core.h>
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#include <plat/adc-core.h>
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static struct map_desc s3c2443_iodesc[] __initdata = {
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static struct map_desc s3c2443_iodesc[] __initdata = {
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IODESC_ENT(WATCHDOG),
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IODESC_ENT(WATCHDOG),
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@ -70,6 +71,8 @@ int __init s3c2443_init(void)
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s3c_nand_setname("s3c2412-nand");
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s3c_nand_setname("s3c2412-nand");
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s3c_fb_setname("s3c2443-fb");
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s3c_fb_setname("s3c2443-fb");
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s3c_adc_setname("s3c2443-adc");
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/* change WDT IRQ number */
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/* change WDT IRQ number */
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s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
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s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
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s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
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s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
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@ -41,6 +41,7 @@
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enum s3c_cpu_type {
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enum s3c_cpu_type {
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TYPE_ADCV1, /* S3C24XX */
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TYPE_ADCV1, /* S3C24XX */
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TYPE_ADCV11, /* S3C2443 */
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TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
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TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
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TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
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TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
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};
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};
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@ -106,6 +107,9 @@ static inline void s3c_adc_select(struct adc_device *adc,
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if (!client->is_ts) {
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if (!client->is_ts) {
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if (cpu == TYPE_ADCV3)
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if (cpu == TYPE_ADCV3)
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writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
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writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
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else if (cpu == TYPE_ADCV11)
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writel(client->channel & 0xf,
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adc->regs + S3C2443_ADCMUX);
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else
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else
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con |= S3C2410_ADCCON_SELMUX(client->channel);
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con |= S3C2410_ADCCON_SELMUX(client->channel);
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}
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}
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@ -294,13 +298,13 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
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client->nr_samples--;
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client->nr_samples--;
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if (cpu != TYPE_ADCV1) {
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if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV11) {
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data0 &= 0x3ff;
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data1 &= 0x3ff;
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} else {
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/* S3C64XX/S5P ADC resolution is 12-bit */
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/* S3C64XX/S5P ADC resolution is 12-bit */
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data0 &= 0xfff;
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data0 &= 0xfff;
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data1 &= 0xfff;
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data1 &= 0xfff;
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} else {
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data0 &= 0x3ff;
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data1 &= 0x3ff;
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}
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}
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if (client->convert_cb)
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if (client->convert_cb)
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@ -321,7 +325,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
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}
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}
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exit:
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exit:
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if (cpu != TYPE_ADCV1) {
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if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3) {
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/* Clear ADC interrupt */
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/* Clear ADC interrupt */
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writel(0, adc->regs + S3C64XX_ADCCLRINT);
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writel(0, adc->regs + S3C64XX_ADCCLRINT);
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}
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}
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@ -492,6 +496,9 @@ static struct platform_device_id s3c_adc_driver_ids[] = {
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{
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{
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.name = "s3c24xx-adc",
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.name = "s3c24xx-adc",
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.driver_data = TYPE_ADCV1,
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.driver_data = TYPE_ADCV1,
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}, {
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.name = "s3c2443-adc",
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.driver_data = TYPE_ADCV11,
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}, {
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}, {
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.name = "s3c64xx-adc",
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.name = "s3c64xx-adc",
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.driver_data = TYPE_ADCV2,
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.driver_data = TYPE_ADCV2,
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