clk: imx: composite-8m: add imx8m_clk_hw_composite_core
There are several clock slices, current composite code only support bus/ip clock slices, it could not support core slice. So introduce a new API imx8m_clk_hw_composite_core to support core slice. To core slice, post divider with 3 bits width and no pre divider. Other fields are same as bus/ip slices. Add a flag IMX_COMPOSITE_CORE for the usecase. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -15,6 +15,7 @@
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#define PCG_PREDIV_MAX 8
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#define PCG_DIV_SHIFT 0
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#define PCG_CORE_DIV_WIDTH 3
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#define PCG_DIV_WIDTH 6
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#define PCG_DIV_MAX 64
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@ -126,6 +127,7 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = {
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struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
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const char * const *parent_names,
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int num_parents, void __iomem *reg,
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u32 composite_flags,
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unsigned long flags)
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{
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struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
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@ -133,6 +135,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
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struct clk_divider *div = NULL;
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struct clk_gate *gate = NULL;
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struct clk_mux *mux = NULL;
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const struct clk_ops *divider_ops;
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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@ -150,8 +153,16 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
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div_hw = &div->hw;
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div->reg = reg;
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div->shift = PCG_PREDIV_SHIFT;
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div->width = PCG_PREDIV_WIDTH;
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if (composite_flags & IMX_COMPOSITE_CORE) {
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div->shift = PCG_DIV_SHIFT;
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div->width = PCG_CORE_DIV_WIDTH;
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divider_ops = &clk_divider_ops;
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} else {
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div->shift = PCG_PREDIV_SHIFT;
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div->width = PCG_PREDIV_WIDTH;
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divider_ops = &imx8m_clk_composite_divider_ops;
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}
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div->lock = &imx_ccm_lock;
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div->flags = CLK_DIVIDER_ROUND_CLOSEST;
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@ -166,8 +177,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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mux_hw, &clk_mux_ops, div_hw,
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&imx8m_clk_composite_divider_ops,
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gate_hw, &clk_gate_ops, flags);
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divider_ops, gate_hw, &clk_gate_ops, flags);
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if (IS_ERR(hw))
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goto fail;
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@ -477,20 +477,29 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
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struct clk *div, struct clk *mux, struct clk *pll,
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struct clk *step);
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#define IMX_COMPOSITE_CORE BIT(0)
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struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
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const char * const *parent_names,
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int num_parents,
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void __iomem *reg,
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u32 composite_flags,
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unsigned long flags);
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#define imx8m_clk_hw_composite_core(name, parent_names, reg) \
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imx8m_clk_hw_composite_flags(name, parent_names, \
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ARRAY_SIZE(parent_names), reg, \
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IMX_COMPOSITE_CORE, \
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CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
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#define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \
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flags) \
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to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
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num_parents, reg, flags))
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num_parents, reg, 0, flags))
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#define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \
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imx8m_clk_hw_composite_flags(name, parent_names, \
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ARRAY_SIZE(parent_names), reg, \
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ARRAY_SIZE(parent_names), reg, 0, \
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flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
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#define __imx8m_clk_composite(name, parent_names, reg, flags) \
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