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drm/tegra: Use tegra_commit_dc() in output drivers 

All output drivers have open-coded variants of this function, so export
it to remove some code duplication.

Signed-off-by: Thierry Reding <treding@nvidia.com>
hifive-unleashed-5.1
Thierry Reding 2014-11-21 17:33:33 +01:00
parent 4cd4df8080
commit 62b9e06321
6 changed files with 11 additions and 18 deletions
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2
drivers/gpu/drm/tegra/dc.c
View File

@ -65,7 +65,7 @@ static void tegra_dc_cursor_commit(struct tegra_dc *dc)
* into the ACTIVE copy, either immediately if the display controller is in
* STOP mode, or at the next frame boundary otherwise.
*/
static void tegra_dc_commit(struct tegra_dc *dc)
void tegra_dc_commit(struct tegra_dc *dc)
{
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);

1
drivers/gpu/drm/tegra/drm.h
View File

@ -177,6 +177,7 @@ struct tegra_dc_window {
void tegra_dc_enable_vblank(struct tegra_dc *dc);
void tegra_dc_disable_vblank(struct tegra_dc *dc);
void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file);
void tegra_dc_commit(struct tegra_dc *dc);
struct tegra_output_ops {
int (*enable)(struct tegra_output *output);

6
drivers/gpu/drm/tegra/dsi.c
View File

@ -658,8 +658,7 @@ static int tegra_output_dsi_enable(struct tegra_output *output)
PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
tegra_dc_commit(dc);
/* enable DSI controller */
tegra_dsi_enable(dsi);
@ -778,8 +777,7 @@ static int tegra_output_dsi_disable(struct tegra_output *output)
value &= ~DSI_ENABLE;
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
tegra_dc_commit(dc);
}
err = tegra_dsi_wait_idle(dsi, 100);

6
drivers/gpu/drm/tegra/hdmi.c
View File

@ -997,8 +997,7 @@ static int tegra_output_hdmi_enable(struct tegra_output *output)
PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
tegra_dc_commit(dc);
/* TODO: add HDCP support */
@ -1042,8 +1041,7 @@ static int tegra_output_hdmi_disable(struct tegra_output *output)
value &= ~HDMI_ENABLE;
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
tegra_dc_commit(dc);
}
clk_disable_unprepare(hdmi->clk);

8
drivers/gpu/drm/tegra/rgb.c
View File

@ -123,8 +123,7 @@ static int tegra_output_rgb_enable(struct tegra_output *output)
PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
tegra_dc_commit(rgb->dc);
rgb->enabled = true;
@ -148,11 +147,10 @@ static int tegra_output_rgb_disable(struct tegra_output *output)
value &= ~DISP_CTRL_MODE_MASK;
tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_COMMAND);
tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
tegra_dc_commit(rgb->dc);
rgb->enabled = false;
return 0;

6
drivers/gpu/drm/tegra/sor.c
View File

@ -267,8 +267,7 @@ static int tegra_sor_wakeup(struct tegra_sor *sor)
PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
tegra_dc_commit(dc);
timeout = jiffies + msecs_to_jiffies(250);
@ -1080,8 +1079,7 @@ static int tegra_output_sor_disable(struct tegra_output *output)
value &= ~SOR_ENABLE;
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
tegra_dc_commit(dc);
}
err = tegra_sor_power_down(sor);