memory: tegra: Changes for v4.16-rc1
The Tegra memory controller driver will now instruct the SMMU driver to create groups, which will make it easier for device drivers to share an IOMMU domain between multiple devices. Initial Tegra186 support is also added in a separate driver. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlo6tlMTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoR7MEACpoyPkV5fGz3z8rdsYaVZSA+upYEHw CC4v5XslNCucmk57XIYTbAZRu7W5MuzP3hq+DoYM5B5EHxgt1a2YHNtjjg3eLx1T U+8hjoOPOYu7FBVmUf4V6Buvmws90DxtfvqcfIScJJEAPgKsT/wfGXNstc88kDnO c+huQxk5QZsyGBgt1sS61zlymaLpDlSoE6kScXnjM1K6XtUdZ+8zmoMdZ7Ka8DUv kwBoYXgUpVminWpSrfuV7f3/8BtTSJ/b2rUPz7Ren0JJTFrhIi/ckeQ5YhTa46Dn oqR0f6MuLRGADT+E5DfoF7otvE2Fvq0Uq/YlypIf9gtiit5mhPM7ZXb3LOwDGiCp 0mwljW9Uov7ZpFnb8b9SlVf1b+zDeeLxtARq4qzgky5OkWZp4hXZw+Os3ebXQYW3 d/MUfwdqgNKOccGRsRkk9OEdUiFGpGtInb0xM9OWBCHvdrXhbK9llZ3wnrE+M3SY BELM+94YorqVPx5JTmiM7kTozVwpkvZQG6kU2J81Y55FI1ELQF7Mk0yzFs562tG5 2abc07xkSUCdC6zsrgNOy+AtuRH8oHccUfZRACLUhzHNCrvfr3MrEcEv8l4VRJp4 ZLfR8UjmtTI8YllBKdSdUtFB4nN5oyoIPCNsgwzXcTnKV5SzAyA/KuDW6IWoNU1L 6ekAxpeiHVnLKA== =ncAl -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.16-memory' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers Pull "memory: tegra: Changes for v4.16-rc1" from Thierry Reding: The Tegra memory controller driver will now instruct the SMMU driver to create groups, which will make it easier for device drivers to share an IOMMU domain between multiple devices. Initial Tegra186 support is also added in a separate driver. * tag 'tegra-for-4.16-memory' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux: iommu/tegra-smmu: Fix return value check in tegra_smmu_group_get() iommu/tegra: Allow devices to be grouped memory: tegra: Create SMMU display groups memory: tegra: Add Tegra186 support dt-bindings: memory: Add Tegra186 support dt-bindings: misc: Add Tegra186 MISC registers bindingshifive-unleashed-5.1
Arnd Bergmann
commit
62bf8ae896
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@ -12,6 +12,8 @@ Required properties:
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- clock-names: Must include the following entries:
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- mc: the module's clock input
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- interrupts: The interrupt outputs from the controller.
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Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:
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- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
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the SWGROUP of the master.
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@ -0,0 +1,12 @@
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NVIDIA Tegra186 MISC register block
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The MISC register block found on Tegra186 SoCs contains registers that can be
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used to identify a given chip and various strapping options.
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Required properties:
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- compatible: Must be:
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- Tegra186: "nvidia,tegra186-misc"
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- reg: Should contain 2 entries: The first entry gives the physical address
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and length of the register region which contains revision and debug
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features. The second entry specifies the physical address and length
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of the register region indicating the strapping options.
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@ -20,6 +20,12 @@
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#include <soc/tegra/ahb.h>
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#include <soc/tegra/mc.h>
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struct tegra_smmu_group {
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struct list_head list;
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const struct tegra_smmu_group_soc *soc;
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struct iommu_group *group;
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};
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struct tegra_smmu {
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void __iomem *regs;
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struct device *dev;
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@ -27,6 +33,8 @@ struct tegra_smmu {
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struct tegra_mc *mc;
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const struct tegra_smmu_soc *soc;
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struct list_head groups;
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unsigned long pfn_mask;
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unsigned long tlb_mask;
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@ -703,19 +711,47 @@ static struct tegra_smmu *tegra_smmu_find(struct device_node *np)
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return mc->smmu;
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}
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static int tegra_smmu_configure(struct tegra_smmu *smmu, struct device *dev,
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struct of_phandle_args *args)
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{
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const struct iommu_ops *ops = smmu->iommu.ops;
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int err;
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err = iommu_fwspec_init(dev, &dev->of_node->fwnode, ops);
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if (err < 0) {
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dev_err(dev, "failed to initialize fwspec: %d\n", err);
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return err;
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}
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err = ops->of_xlate(dev, args);
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if (err < 0) {
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dev_err(dev, "failed to parse SW group ID: %d\n", err);
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iommu_fwspec_free(dev);
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return err;
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}
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return 0;
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}
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static int tegra_smmu_add_device(struct device *dev)
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{
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struct device_node *np = dev->of_node;
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struct tegra_smmu *smmu = NULL;
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struct iommu_group *group;
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struct of_phandle_args args;
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unsigned int index = 0;
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int err;
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while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
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&args) == 0) {
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struct tegra_smmu *smmu;
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smmu = tegra_smmu_find(args.np);
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if (smmu) {
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err = tegra_smmu_configure(smmu, dev, &args);
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of_node_put(args.np);
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if (err < 0)
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return err;
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/*
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* Only a single IOMMU master interface is currently
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* supported by the Linux kernel, so abort after the
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@ -728,9 +764,13 @@ static int tegra_smmu_add_device(struct device *dev)
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break;
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}
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of_node_put(args.np);
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index++;
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}
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if (!smmu)
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return -ENODEV;
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group = iommu_group_get_for_dev(dev);
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if (IS_ERR(group))
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return PTR_ERR(group);
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@ -751,6 +791,80 @@ static void tegra_smmu_remove_device(struct device *dev)
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iommu_group_remove_device(dev);
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}
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static const struct tegra_smmu_group_soc *
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tegra_smmu_find_group(struct tegra_smmu *smmu, unsigned int swgroup)
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{
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unsigned int i, j;
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for (i = 0; i < smmu->soc->num_groups; i++)
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for (j = 0; j < smmu->soc->groups[i].num_swgroups; j++)
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if (smmu->soc->groups[i].swgroups[j] == swgroup)
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return &smmu->soc->groups[i];
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return NULL;
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}
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static struct iommu_group *tegra_smmu_group_get(struct tegra_smmu *smmu,
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unsigned int swgroup)
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{
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const struct tegra_smmu_group_soc *soc;
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struct tegra_smmu_group *group;
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soc = tegra_smmu_find_group(smmu, swgroup);
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if (!soc)
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return NULL;
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mutex_lock(&smmu->lock);
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list_for_each_entry(group, &smmu->groups, list)
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if (group->soc == soc) {
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mutex_unlock(&smmu->lock);
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return group->group;
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}
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group = devm_kzalloc(smmu->dev, sizeof(*group), GFP_KERNEL);
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if (!group) {
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mutex_unlock(&smmu->lock);
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return NULL;
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}
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INIT_LIST_HEAD(&group->list);
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group->soc = soc;
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group->group = iommu_group_alloc();
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if (IS_ERR(group->group)) {
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devm_kfree(smmu->dev, group);
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mutex_unlock(&smmu->lock);
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return NULL;
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}
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list_add_tail(&group->list, &smmu->groups);
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mutex_unlock(&smmu->lock);
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return group->group;
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}
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static struct iommu_group *tegra_smmu_device_group(struct device *dev)
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{
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struct iommu_fwspec *fwspec = dev->iommu_fwspec;
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struct tegra_smmu *smmu = dev->archdata.iommu;
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struct iommu_group *group;
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group = tegra_smmu_group_get(smmu, fwspec->ids[0]);
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if (!group)
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group = generic_device_group(dev);
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return group;
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}
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static int tegra_smmu_of_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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u32 id = args->args[0];
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return iommu_fwspec_add_ids(dev, &id, 1);
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}
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static const struct iommu_ops tegra_smmu_ops = {
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.capable = tegra_smmu_capable,
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.domain_alloc = tegra_smmu_domain_alloc,
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@ -759,12 +873,12 @@ static const struct iommu_ops tegra_smmu_ops = {
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.detach_dev = tegra_smmu_detach_dev,
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.add_device = tegra_smmu_add_device,
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.remove_device = tegra_smmu_remove_device,
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.device_group = generic_device_group,
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.device_group = tegra_smmu_device_group,
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.map = tegra_smmu_map,
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.unmap = tegra_smmu_unmap,
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.map_sg = default_iommu_map_sg,
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.iova_to_phys = tegra_smmu_iova_to_phys,
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.of_xlate = tegra_smmu_of_xlate,
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.pgsize_bitmap = SZ_4K,
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};
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@ -913,6 +1027,7 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev,
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if (!smmu->asids)
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return ERR_PTR(-ENOMEM);
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INIT_LIST_HEAD(&smmu->groups);
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mutex_init(&smmu->lock);
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smmu->regs = mc->regs;
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@ -954,6 +1069,7 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev,
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return ERR_PTR(err);
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iommu_device_set_ops(&smmu->iommu, &tegra_smmu_ops);
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iommu_device_set_fwnode(&smmu->iommu, dev->fwnode);
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err = iommu_device_register(&smmu->iommu);
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if (err) {
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@ -10,3 +10,4 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
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obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
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obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
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obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
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@ -912,11 +912,26 @@ static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
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{ .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
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};
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static const unsigned int tegra114_group_display[] = {
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TEGRA_SWGROUP_DC,
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TEGRA_SWGROUP_DCB,
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};
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static const struct tegra_smmu_group_soc tegra114_groups[] = {
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{
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.name = "display",
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.swgroups = tegra114_group_display,
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.num_swgroups = ARRAY_SIZE(tegra114_group_display),
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},
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};
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static const struct tegra_smmu_soc tegra114_smmu_soc = {
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.clients = tegra114_mc_clients,
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.num_clients = ARRAY_SIZE(tegra114_mc_clients),
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.swgroups = tegra114_swgroups,
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.num_swgroups = ARRAY_SIZE(tegra114_swgroups),
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.groups = tegra114_groups,
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.num_groups = ARRAY_SIZE(tegra114_groups),
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.supports_round_robin_arbitration = false,
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.supports_request_limit = false,
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.num_tlb_lines = 32,
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@ -999,12 +999,27 @@ static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
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{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
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};
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static const unsigned int tegra124_group_display[] = {
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TEGRA_SWGROUP_DC,
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TEGRA_SWGROUP_DCB,
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};
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static const struct tegra_smmu_group_soc tegra124_groups[] = {
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{
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.name = "display",
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.swgroups = tegra124_group_display,
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.num_swgroups = ARRAY_SIZE(tegra124_group_display),
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},
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};
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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static const struct tegra_smmu_soc tegra124_smmu_soc = {
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.clients = tegra124_mc_clients,
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.num_clients = ARRAY_SIZE(tegra124_mc_clients),
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.swgroups = tegra124_swgroups,
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.num_swgroups = ARRAY_SIZE(tegra124_swgroups),
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.groups = tegra124_groups,
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.num_groups = ARRAY_SIZE(tegra124_groups),
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.supports_round_robin_arbitration = true,
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.supports_request_limit = true,
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.num_tlb_lines = 32,
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@ -1029,6 +1044,8 @@ static const struct tegra_smmu_soc tegra132_smmu_soc = {
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.num_clients = ARRAY_SIZE(tegra124_mc_clients),
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.swgroups = tegra124_swgroups,
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.num_swgroups = ARRAY_SIZE(tegra124_swgroups),
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.groups = tegra124_groups,
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.num_groups = ARRAY_SIZE(tegra124_groups),
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.supports_round_robin_arbitration = true,
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.supports_request_limit = true,
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.num_tlb_lines = 32,
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@ -0,0 +1,600 @@
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/*
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* Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/memory/tegra186-mc.h>
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struct tegra_mc {
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struct device *dev;
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void __iomem *regs;
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};
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struct tegra_mc_client {
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const char *name;
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unsigned int sid;
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struct {
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unsigned int override;
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unsigned int security;
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} regs;
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};
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static const struct tegra_mc_client tegra186_mc_clients[] = {
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{
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.name = "ptcr",
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.sid = TEGRA186_SID_PASSTHROUGH,
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.regs = {
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.override = 0x000,
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.security = 0x004,
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},
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}, {
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.name = "afir",
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.sid = TEGRA186_SID_AFI,
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.regs = {
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.override = 0x070,
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.security = 0x074,
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},
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}, {
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.name = "hdar",
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.sid = TEGRA186_SID_HDA,
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.regs = {
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.override = 0x0a8,
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.security = 0x0ac,
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},
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}, {
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.name = "host1xdmar",
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.sid = TEGRA186_SID_HOST1X,
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.regs = {
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.override = 0x0b0,
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.security = 0x0b4,
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},
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}, {
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.name = "nvencsrd",
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.sid = TEGRA186_SID_NVENC,
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.regs = {
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.override = 0x0e0,
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.security = 0x0e4,
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},
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}, {
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.name = "satar",
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.sid = TEGRA186_SID_SATA,
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.regs = {
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.override = 0x0f8,
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.security = 0x0fc,
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},
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}, {
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.name = "mpcorer",
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.sid = TEGRA186_SID_PASSTHROUGH,
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.regs = {
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.override = 0x138,
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.security = 0x13c,
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},
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}, {
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.name = "nvencswr",
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.sid = TEGRA186_SID_NVENC,
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.regs = {
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.override = 0x158,
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.security = 0x15c,
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},
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}, {
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.name = "afiw",
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.sid = TEGRA186_SID_AFI,
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.regs = {
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.override = 0x188,
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.security = 0x18c,
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},
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}, {
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.name = "hdaw",
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.sid = TEGRA186_SID_HDA,
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.regs = {
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.override = 0x1a8,
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.security = 0x1ac,
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},
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}, {
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.name = "mpcorew",
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.sid = TEGRA186_SID_PASSTHROUGH,
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.regs = {
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.override = 0x1c8,
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.security = 0x1cc,
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},
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}, {
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.name = "sataw",
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.sid = TEGRA186_SID_SATA,
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.regs = {
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.override = 0x1e8,
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.security = 0x1ec,
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},
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}, {
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.name = "ispra",
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.sid = TEGRA186_SID_ISP,
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.regs = {
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.override = 0x220,
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.security = 0x224,
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},
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}, {
|
||||
.name = "ispwa",
|
||||
.sid = TEGRA186_SID_ISP,
|
||||
.regs = {
|
||||
.override = 0x230,
|
||||
.security = 0x234,
|
||||
},
|
||||
}, {
|
||||
.name = "ispwb",
|
||||
.sid = TEGRA186_SID_ISP,
|
||||
.regs = {
|
||||
.override = 0x238,
|
||||
.security = 0x23c,
|
||||
},
|
||||
}, {
|
||||
.name = "xusb_hostr",
|
||||
.sid = TEGRA186_SID_XUSB_HOST,
|
||||
.regs = {
|
||||
.override = 0x250,
|
||||
.security = 0x254,
|
||||
},
|
||||
}, {
|
||||
.name = "xusb_hostw",
|
||||
.sid = TEGRA186_SID_XUSB_HOST,
|
||||
.regs = {
|
||||
.override = 0x258,
|
||||
.security = 0x25c,
|
||||
},
|
||||
}, {
|
||||
.name = "xusb_devr",
|
||||
.sid = TEGRA186_SID_XUSB_DEV,
|
||||
.regs = {
|
||||
.override = 0x260,
|
||||
.security = 0x264,
|
||||
},
|
||||
}, {
|
||||
.name = "xusb_devw",
|
||||
.sid = TEGRA186_SID_XUSB_DEV,
|
||||
.regs = {
|
||||
.override = 0x268,
|
||||
.security = 0x26c,
|
||||
},
|
||||
}, {
|
||||
.name = "tsecsrd",
|
||||
.sid = TEGRA186_SID_TSEC,
|
||||
.regs = {
|
||||
.override = 0x2a0,
|
||||
.security = 0x2a4,
|
||||
},
|
||||
}, {
|
||||
.name = "tsecswr",
|
||||
.sid = TEGRA186_SID_TSEC,
|
||||
.regs = {
|
||||
.override = 0x2a8,
|
||||
.security = 0x2ac,
|
||||
},
|
||||
}, {
|
||||
.name = "gpusrd",
|
||||
.sid = TEGRA186_SID_GPU,
|
||||
.regs = {
|
||||
.override = 0x2c0,
|
||||
.security = 0x2c4,
|
||||
},
|
||||
}, {
|
||||
.name = "gpuswr",
|
||||
.sid = TEGRA186_SID_GPU,
|
||||
.regs = {
|
||||
.override = 0x2c8,
|
||||
.security = 0x2cc,
|
||||
},
|
||||
}, {
|
||||
.name = "sdmmcra",
|
||||
.sid = TEGRA186_SID_SDMMC1,
|
||||
.regs = {
|
||||
.override = 0x300,
|
||||
.security = 0x304,
|
||||
},
|
||||
}, {
|
||||
.name = "sdmmcraa",
|
||||
.sid = TEGRA186_SID_SDMMC2,
|
||||
.regs = {
|
||||
.override = 0x308,
|
||||
.security = 0x30c,
|
||||
},
|
||||
}, {
|
||||
.name = "sdmmcr",
|
||||
.sid = TEGRA186_SID_SDMMC3,
|
||||
.regs = {
|
||||
.override = 0x310,
|
||||
.security = 0x314,
|
||||
},
|
||||
}, {
|
||||
.name = "sdmmcrab",
|
||||
.sid = TEGRA186_SID_SDMMC4,
|
||||
.regs = {
|
||||
.override = 0x318,
|
||||
.security = 0x31c,
|
||||
},
|
||||
}, {
|
||||
.name = "sdmmcwa",
|
||||
.sid = TEGRA186_SID_SDMMC1,
|
||||
.regs = {
|
||||
.override = 0x320,
|
||||
.security = 0x324,
|
||||
},
|
||||
}, {
|
||||
.name = "sdmmcwaa",
|
||||
.sid = TEGRA186_SID_SDMMC2,
|
||||
.regs = {
|
||||
.override = 0x328,
|
||||
.security = 0x32c,
|
||||
},
|
||||
}, {
|
||||
.name = "sdmmcw",
|
||||
.sid = TEGRA186_SID_SDMMC3,
|
||||
.regs = {
|
||||
.override = 0x330,
|
||||
.security = 0x334,
|
||||
},
|
||||
}, {
|
||||
.name = "sdmmcwab",
|
||||
.sid = TEGRA186_SID_SDMMC4,
|
||||
.regs = {
|
||||
.override = 0x338,
|
||||
.security = 0x33c,
|
||||
},
|
||||
}, {
|
||||
.name = "vicsrd",
|
||||
.sid = TEGRA186_SID_VIC,
|
||||
.regs = {
|
||||
.override = 0x360,
|
||||
.security = 0x364,
|
||||
},
|
||||
}, {
|
||||
.name = "vicswr",
|
||||
.sid = TEGRA186_SID_VIC,
|
||||
.regs = {
|
||||
.override = 0x368,
|
||||
.security = 0x36c,
|
||||
},
|
||||
}, {
|
||||
.name = "viw",
|
||||
.sid = TEGRA186_SID_VI,
|
||||
.regs = {
|
||||
.override = 0x390,
|
||||
.security = 0x394,
|
||||
},
|
||||
}, {
|
||||
.name = "nvdecsrd",
|
||||
.sid = TEGRA186_SID_NVDEC,
|
||||
.regs = {
|
||||
.override = 0x3c0,
|
||||
.security = 0x3c4,
|
||||
},
|
||||
}, {
|
||||
.name = "nvdecswr",
|
||||
.sid = TEGRA186_SID_NVDEC,
|
||||
.regs = {
|
||||
.override = 0x3c8,
|
||||
.security = 0x3cc,
|
||||
},
|
||||
}, {
|
||||
.name = "aper",
|
||||
.sid = TEGRA186_SID_APE,
|
||||
.regs = {
|
||||
.override = 0x3d0,
|
||||
.security = 0x3d4,
|
||||
},
|
||||
}, {
|
||||
.name = "apew",
|
||||
.sid = TEGRA186_SID_APE,
|
||||
.regs = {
|
||||
.override = 0x3d8,
|
||||
.security = 0x3dc,
|
||||
},
|
||||
}, {
|
||||
.name = "nvjpgsrd",
|
||||
.sid = TEGRA186_SID_NVJPG,
|
||||
.regs = {
|
||||
.override = 0x3f0,
|
||||
.security = 0x3f4,
|
||||
},
|
||||
}, {
|
||||
.name = "nvjpgswr",
|
||||
.sid = TEGRA186_SID_NVJPG,
|
||||
.regs = {
|
||||
.override = 0x3f8,
|
||||
.security = 0x3fc,
|
||||
},
|
||||
}, {
|
||||
.name = "sesrd",
|
||||
.sid = TEGRA186_SID_SE,
|
||||
.regs = {
|
||||
.override = 0x400,
|
||||
.security = 0x404,
|
||||
},
|
||||
}, {
|
||||
.name = "seswr",
|
||||
.sid = TEGRA186_SID_SE,
|
||||
.regs = {
|
||||
.override = 0x408,
|
||||
.security = 0x40c,
|
||||
},
|
||||
}, {
|
||||
.name = "etrr",
|
||||
.sid = TEGRA186_SID_ETR,
|
||||
.regs = {
|
||||
.override = 0x420,
|
||||
.security = 0x424,
|
||||
},
|
||||
}, {
|
||||
.name = "etrw",
|
||||
.sid = TEGRA186_SID_ETR,
|
||||
.regs = {
|
||||
.override = 0x428,
|
||||
.security = 0x42c,
|
||||
},
|
||||
}, {
|
||||
.name = "tsecsrdb",
|
||||
.sid = TEGRA186_SID_TSECB,
|
||||
.regs = {
|
||||
.override = 0x430,
|
||||
.security = 0x434,
|
||||
},
|
||||
}, {
|
||||
.name = "tsecswrb",
|
||||
.sid = TEGRA186_SID_TSECB,
|
||||
.regs = {
|
||||
.override = 0x438,
|
||||
.security = 0x43c,
|
||||
},
|
||||
}, {
|
||||
.name = "gpusrd2",
|
||||
.sid = TEGRA186_SID_GPU,
|
||||
.regs = {
|
||||
.override = 0x440,
|
||||
.security = 0x444,
|
||||
},
|
||||
}, {
|
||||
.name = "gpuswr2",
|
||||
.sid = TEGRA186_SID_GPU,
|
||||
.regs = {
|
||||
.override = 0x448,
|
||||
.security = 0x44c,
|
||||
},
|
||||
}, {
|
||||
.name = "axisr",
|
||||
.sid = TEGRA186_SID_GPCDMA_0,
|
||||
.regs = {
|
||||
.override = 0x460,
|
||||
.security = 0x464,
|
||||
},
|
||||
}, {
|
||||
.name = "axisw",
|
||||
.sid = TEGRA186_SID_GPCDMA_0,
|
||||
.regs = {
|
||||
.override = 0x468,
|
||||
.security = 0x46c,
|
||||
},
|
||||
}, {
|
||||
.name = "eqosr",
|
||||
.sid = TEGRA186_SID_EQOS,
|
||||
.regs = {
|
||||
.override = 0x470,
|
||||
.security = 0x474,
|
||||
},
|
||||
}, {
|
||||
.name = "eqosw",
|
||||
.sid = TEGRA186_SID_EQOS,
|
||||
.regs = {
|
||||
.override = 0x478,
|
||||
.security = 0x47c,
|
||||
},
|
||||
}, {
|
||||
.name = "ufshcr",
|
||||
.sid = TEGRA186_SID_UFSHC,
|
||||
.regs = {
|
||||
.override = 0x480,
|
||||
.security = 0x484,
|
||||
},
|
||||
}, {
|
||||
.name = "ufshcw",
|
||||
.sid = TEGRA186_SID_UFSHC,
|
||||
.regs = {
|
||||
.override = 0x488,
|
||||
.security = 0x48c,
|
||||
},
|
||||
}, {
|
||||
.name = "nvdisplayr",
|
||||
.sid = TEGRA186_SID_NVDISPLAY,
|
||||
.regs = {
|
||||
.override = 0x490,
|
||||
.security = 0x494,
|
||||
},
|
||||
}, {
|
||||
.name = "bpmpr",
|
||||
.sid = TEGRA186_SID_BPMP,
|
||||
.regs = {
|
||||
.override = 0x498,
|
||||
.security = 0x49c,
|
||||
},
|
||||
}, {
|
||||
.name = "bpmpw",
|
||||
.sid = TEGRA186_SID_BPMP,
|
||||
.regs = {
|
||||
.override = 0x4a0,
|
||||
.security = 0x4a4,
|
||||
},
|
||||
}, {
|
||||
.name = "bpmpdmar",
|
||||
.sid = TEGRA186_SID_BPMP,
|
||||
.regs = {
|
||||
.override = 0x4a8,
|
||||
.security = 0x4ac,
|
||||
},
|
||||
}, {
|
||||
.name = "bpmpdmaw",
|
||||
.sid = TEGRA186_SID_BPMP,
|
||||
.regs = {
|
||||
.override = 0x4b0,
|
||||
.security = 0x4b4,
|
||||
},
|
||||
}, {
|
||||
.name = "aonr",
|
||||
.sid = TEGRA186_SID_AON,
|
||||
.regs = {
|
||||
.override = 0x4b8,
|
||||
.security = 0x4bc,
|
||||
},
|
||||
}, {
|
||||
.name = "aonw",
|
||||
.sid = TEGRA186_SID_AON,
|
||||
.regs = {
|
||||
.override = 0x4c0,
|
||||
.security = 0x4c4,
|
||||
},
|
||||
}, {
|
||||
.name = "aondmar",
|
||||
.sid = TEGRA186_SID_AON,
|
||||
.regs = {
|
||||
.override = 0x4c8,
|
||||
.security = 0x4cc,
|
||||
},
|
||||
}, {
|
||||
.name = "aondmaw",
|
||||
.sid = TEGRA186_SID_AON,
|
||||
.regs = {
|
||||
.override = 0x4d0,
|
||||
.security = 0x4d4,
|
||||
},
|
||||
}, {
|
||||
.name = "scer",
|
||||
.sid = TEGRA186_SID_SCE,
|
||||
.regs = {
|
||||
.override = 0x4d8,
|
||||
.security = 0x4dc,
|
||||
},
|
||||
}, {
|
||||
.name = "scew",
|
||||
.sid = TEGRA186_SID_SCE,
|
||||
.regs = {
|
||||
.override = 0x4e0,
|
||||
.security = 0x4e4,
|
||||
},
|
||||
}, {
|
||||
.name = "scedmar",
|
||||
.sid = TEGRA186_SID_SCE,
|
||||
.regs = {
|
||||
.override = 0x4e8,
|
||||
.security = 0x4ec,
|
||||
},
|
||||
}, {
|
||||
.name = "scedmaw",
|
||||
.sid = TEGRA186_SID_SCE,
|
||||
.regs = {
|
||||
.override = 0x4f0,
|
||||
.security = 0x4f4,
|
||||
},
|
||||
}, {
|
||||
.name = "apedmar",
|
||||
.sid = TEGRA186_SID_APE,
|
||||
.regs = {
|
||||
.override = 0x4f8,
|
||||
.security = 0x4fc,
|
||||
},
|
||||
}, {
|
||||
.name = "apedmaw",
|
||||
.sid = TEGRA186_SID_APE,
|
||||
.regs = {
|
||||
.override = 0x500,
|
||||
.security = 0x504,
|
||||
},
|
||||
}, {
|
||||
.name = "nvdisplayr1",
|
||||
.sid = TEGRA186_SID_NVDISPLAY,
|
||||
.regs = {
|
||||
.override = 0x508,
|
||||
.security = 0x50c,
|
||||
},
|
||||
}, {
|
||||
.name = "vicsrd1",
|
||||
.sid = TEGRA186_SID_VIC,
|
||||
.regs = {
|
||||
.override = 0x510,
|
||||
.security = 0x514,
|
||||
},
|
||||
}, {
|
||||
.name = "nvdecsrd1",
|
||||
.sid = TEGRA186_SID_NVDEC,
|
||||
.regs = {
|
||||
.override = 0x518,
|
||||
.security = 0x51c,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static int tegra186_mc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
struct tegra_mc *mc;
|
||||
unsigned int i;
|
||||
int err = 0;
|
||||
|
||||
mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
|
||||
if (!mc)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
mc->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(mc->regs))
|
||||
return PTR_ERR(mc->regs);
|
||||
|
||||
mc->dev = &pdev->dev;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(tegra186_mc_clients); i++) {
|
||||
const struct tegra_mc_client *client = &tegra186_mc_clients[i];
|
||||
u32 override, security;
|
||||
|
||||
override = readl(mc->regs + client->regs.override);
|
||||
security = readl(mc->regs + client->regs.security);
|
||||
|
||||
dev_dbg(&pdev->dev, "client %s: override: %x security: %x\n",
|
||||
client->name, override, security);
|
||||
|
||||
dev_dbg(&pdev->dev, "setting SID %u for %s\n", client->sid,
|
||||
client->name);
|
||||
writel(client->sid, mc->regs + client->regs.override);
|
||||
|
||||
override = readl(mc->regs + client->regs.override);
|
||||
security = readl(mc->regs + client->regs.security);
|
||||
|
||||
dev_dbg(&pdev->dev, "client %s: override: %x security: %x\n",
|
||||
client->name, override, security);
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, mc);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra186_mc_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra186-mc", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tegra186_mc_of_match);
|
||||
|
||||
static struct platform_driver tegra186_mc_driver = {
|
||||
.driver = {
|
||||
.name = "tegra186-mc",
|
||||
.of_match_table = tegra186_mc_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.prevent_deferred_probe = true,
|
||||
.probe = tegra186_mc_probe,
|
||||
};
|
||||
module_platform_driver(tegra186_mc_driver);
|
||||
|
||||
MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
|
||||
MODULE_DESCRIPTION("NVIDIA Tegra186 Memory Controller driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -1059,11 +1059,26 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
|
|||
{ .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
|
||||
};
|
||||
|
||||
static const unsigned int tegra210_group_display[] = {
|
||||
TEGRA_SWGROUP_DC,
|
||||
TEGRA_SWGROUP_DCB,
|
||||
};
|
||||
|
||||
static const struct tegra_smmu_group_soc tegra210_groups[] = {
|
||||
{
|
||||
.name = "display",
|
||||
.swgroups = tegra210_group_display,
|
||||
.num_swgroups = ARRAY_SIZE(tegra210_group_display),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct tegra_smmu_soc tegra210_smmu_soc = {
|
||||
.clients = tegra210_mc_clients,
|
||||
.num_clients = ARRAY_SIZE(tegra210_mc_clients),
|
||||
.swgroups = tegra210_swgroups,
|
||||
.num_swgroups = ARRAY_SIZE(tegra210_swgroups),
|
||||
.groups = tegra210_groups,
|
||||
.num_groups = ARRAY_SIZE(tegra210_groups),
|
||||
.supports_round_robin_arbitration = true,
|
||||
.supports_request_limit = true,
|
||||
.num_tlb_lines = 32,
|
||||
|
|
|
|||
|
|
@ -934,11 +934,26 @@ static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
|
|||
{ .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
|
||||
};
|
||||
|
||||
static const unsigned int tegra30_group_display[] = {
|
||||
TEGRA_SWGROUP_DC,
|
||||
TEGRA_SWGROUP_DCB,
|
||||
};
|
||||
|
||||
static const struct tegra_smmu_group_soc tegra30_groups[] = {
|
||||
{
|
||||
.name = "display",
|
||||
.swgroups = tegra30_group_display,
|
||||
.num_swgroups = ARRAY_SIZE(tegra30_group_display),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct tegra_smmu_soc tegra30_smmu_soc = {
|
||||
.clients = tegra30_mc_clients,
|
||||
.num_clients = ARRAY_SIZE(tegra30_mc_clients),
|
||||
.swgroups = tegra30_swgroups,
|
||||
.num_swgroups = ARRAY_SIZE(tegra30_swgroups),
|
||||
.groups = tegra30_groups,
|
||||
.num_groups = ARRAY_SIZE(tegra30_groups),
|
||||
.supports_round_robin_arbitration = false,
|
||||
.supports_request_limit = false,
|
||||
.num_tlb_lines = 16,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,111 @@
|
|||
#ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H
|
||||
#define DT_BINDINGS_MEMORY_TEGRA186_MC_H
|
||||
|
||||
/* special clients */
|
||||
#define TEGRA186_SID_INVALID 0x00
|
||||
#define TEGRA186_SID_PASSTHROUGH 0x7f
|
||||
|
||||
/* host1x clients */
|
||||
#define TEGRA186_SID_HOST1X 0x01
|
||||
#define TEGRA186_SID_CSI 0x02
|
||||
#define TEGRA186_SID_VIC 0x03
|
||||
#define TEGRA186_SID_VI 0x04
|
||||
#define TEGRA186_SID_ISP 0x05
|
||||
#define TEGRA186_SID_NVDEC 0x06
|
||||
#define TEGRA186_SID_NVENC 0x07
|
||||
#define TEGRA186_SID_NVJPG 0x08
|
||||
#define TEGRA186_SID_NVDISPLAY 0x09
|
||||
#define TEGRA186_SID_TSEC 0x0a
|
||||
#define TEGRA186_SID_TSECB 0x0b
|
||||
#define TEGRA186_SID_SE 0x0c
|
||||
#define TEGRA186_SID_SE1 0x0d
|
||||
#define TEGRA186_SID_SE2 0x0e
|
||||
#define TEGRA186_SID_SE3 0x0f
|
||||
|
||||
/* GPU clients */
|
||||
#define TEGRA186_SID_GPU 0x10
|
||||
|
||||
/* other SoC clients */
|
||||
#define TEGRA186_SID_AFI 0x11
|
||||
#define TEGRA186_SID_HDA 0x12
|
||||
#define TEGRA186_SID_ETR 0x13
|
||||
#define TEGRA186_SID_EQOS 0x14
|
||||
#define TEGRA186_SID_UFSHC 0x15
|
||||
#define TEGRA186_SID_AON 0x16
|
||||
#define TEGRA186_SID_SDMMC4 0x17
|
||||
#define TEGRA186_SID_SDMMC3 0x18
|
||||
#define TEGRA186_SID_SDMMC2 0x19
|
||||
#define TEGRA186_SID_SDMMC1 0x1a
|
||||
#define TEGRA186_SID_XUSB_HOST 0x1b
|
||||
#define TEGRA186_SID_XUSB_DEV 0x1c
|
||||
#define TEGRA186_SID_SATA 0x1d
|
||||
#define TEGRA186_SID_APE 0x1e
|
||||
#define TEGRA186_SID_SCE 0x1f
|
||||
|
||||
/* GPC DMA clients */
|
||||
#define TEGRA186_SID_GPCDMA_0 0x20
|
||||
#define TEGRA186_SID_GPCDMA_1 0x21
|
||||
#define TEGRA186_SID_GPCDMA_2 0x22
|
||||
#define TEGRA186_SID_GPCDMA_3 0x23
|
||||
#define TEGRA186_SID_GPCDMA_4 0x24
|
||||
#define TEGRA186_SID_GPCDMA_5 0x25
|
||||
#define TEGRA186_SID_GPCDMA_6 0x26
|
||||
#define TEGRA186_SID_GPCDMA_7 0x27
|
||||
|
||||
/* APE DMA clients */
|
||||
#define TEGRA186_SID_APE_1 0x28
|
||||
#define TEGRA186_SID_APE_2 0x29
|
||||
|
||||
/* camera RTCPU */
|
||||
#define TEGRA186_SID_RCE 0x2a
|
||||
|
||||
/* camera RTCPU on host1x address space */
|
||||
#define TEGRA186_SID_RCE_1X 0x2b
|
||||
|
||||
/* APE DMA clients */
|
||||
#define TEGRA186_SID_APE_3 0x2c
|
||||
|
||||
/* camera RTCPU running on APE */
|
||||
#define TEGRA186_SID_APE_CAM 0x2d
|
||||
#define TEGRA186_SID_APE_CAM_1X 0x2e
|
||||
|
||||
/*
|
||||
* The BPMP has its SID value hardcoded in the firmware. Changing it requires
|
||||
* considerable effort.
|
||||
*/
|
||||
#define TEGRA186_SID_BPMP 0x32
|
||||
|
||||
/* for SMMU tests */
|
||||
#define TEGRA186_SID_SMMU_TEST 0x33
|
||||
|
||||
/* host1x virtualization channels */
|
||||
#define TEGRA186_SID_HOST1X_CTX0 0x38
|
||||
#define TEGRA186_SID_HOST1X_CTX1 0x39
|
||||
#define TEGRA186_SID_HOST1X_CTX2 0x3a
|
||||
#define TEGRA186_SID_HOST1X_CTX3 0x3b
|
||||
#define TEGRA186_SID_HOST1X_CTX4 0x3c
|
||||
#define TEGRA186_SID_HOST1X_CTX5 0x3d
|
||||
#define TEGRA186_SID_HOST1X_CTX6 0x3e
|
||||
#define TEGRA186_SID_HOST1X_CTX7 0x3f
|
||||
|
||||
/* host1x command buffers */
|
||||
#define TEGRA186_SID_HOST1X_VM0 0x40
|
||||
#define TEGRA186_SID_HOST1X_VM1 0x41
|
||||
#define TEGRA186_SID_HOST1X_VM2 0x42
|
||||
#define TEGRA186_SID_HOST1X_VM3 0x43
|
||||
#define TEGRA186_SID_HOST1X_VM4 0x44
|
||||
#define TEGRA186_SID_HOST1X_VM5 0x45
|
||||
#define TEGRA186_SID_HOST1X_VM6 0x46
|
||||
#define TEGRA186_SID_HOST1X_VM7 0x47
|
||||
|
||||
/* SE data buffers */
|
||||
#define TEGRA186_SID_SE_VM0 0x48
|
||||
#define TEGRA186_SID_SE_VM1 0x49
|
||||
#define TEGRA186_SID_SE_VM2 0x4a
|
||||
#define TEGRA186_SID_SE_VM3 0x4b
|
||||
#define TEGRA186_SID_SE_VM4 0x4c
|
||||
#define TEGRA186_SID_SE_VM5 0x4d
|
||||
#define TEGRA186_SID_SE_VM6 0x4e
|
||||
#define TEGRA186_SID_SE_VM7 0x4f
|
||||
|
||||
#endif
|
||||
|
|
@ -51,6 +51,12 @@ struct tegra_smmu_swgroup {
|
|||
unsigned int reg;
|
||||
};
|
||||
|
||||
struct tegra_smmu_group_soc {
|
||||
const char *name;
|
||||
const unsigned int *swgroups;
|
||||
unsigned int num_swgroups;
|
||||
};
|
||||
|
||||
struct tegra_smmu_soc {
|
||||
const struct tegra_mc_client *clients;
|
||||
unsigned int num_clients;
|
||||
|
|
@ -58,6 +64,9 @@ struct tegra_smmu_soc {
|
|||
const struct tegra_smmu_swgroup *swgroups;
|
||||
unsigned int num_swgroups;
|
||||
|
||||
const struct tegra_smmu_group_soc *groups;
|
||||
unsigned int num_groups;
|
||||
|
||||
bool supports_round_robin_arbitration;
|
||||
bool supports_request_limit;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue