drm/edid: detect SCDC support in HF-VSDB
This patch does following: - Adds a new structure (drm_hdmi_info) in drm_display_info. This structure will be used to save and indicate if sink supports advanced HDMI 2.0 features - Adds another structure drm_scdc within drm_hdmi_info, to reflect scdc support and capabilities in connected HDMI 2.0 sink. - Checks the HF-VSDB block for presence of SCDC, and marks it in scdc structure - If SCDC is present, checks if sink is capable of generating SCDC read request, and marks it in scdc structure. V2: Addressed review comments Thierry: - Fix typos in commit message and make abbreviation consistent across the commit message. - Change structure object name from hdmi_info -> hdmi - Fix typos and abbreviations in description of structure drm_hdmi_info end the description with a full stop. - Create a structure drm_scdc, and keep all information related to SCDC register set (supported, read request supported) etc in it. Ville: - Change rr -> read_request - Call drm_detect_scrambling function drm_parse_hf_vsdb so that all of HF-VSDB parsing can be kept in same function, in incremental patches. V3: Rebase. V4: Rebase. V5: Rebase. V6: Addressed review comments from Ville - Add clock rate calculations for 1/10 and 1/40 ratios - Remove leftovers from old patchset V7: Added R-B from Jose. V8: Rebase. V9: Rebase. V10: Rebase. Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-5-git-send-email-shashank.sharma@intel.com
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@ -37,6 +37,7 @@
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#include <drm/drm_edid.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_displayid.h>
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#include <drm/drm_scdc_helper.h>
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#include "drm_crtc_internal.h"
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@ -3817,13 +3818,43 @@ EXPORT_SYMBOL(drm_default_rgb_quant_range);
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static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
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const u8 *hf_vsdb)
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{
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struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
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struct drm_display_info *display = &connector->display_info;
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struct drm_hdmi_info *hdmi = &display->hdmi;
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if (hf_vsdb[6] & 0x80) {
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hdmi->scdc.supported = true;
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if (hf_vsdb[6] & 0x40)
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hdmi->scdc.read_request = true;
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}
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/*
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* All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
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* And as per the spec, three factors confirm this:
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* * Availability of a HF-VSDB block in EDID (check)
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* * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
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* * SCDC support available (let's check)
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* Lets check it out.
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*/
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if (hf_vsdb[5]) {
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/* max clock is 5000 KHz times block value */
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u32 max_tmds_clock = hf_vsdb[5] * 5000;
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struct drm_scdc *scdc = &hdmi->scdc;
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if (max_tmds_clock > 340000) {
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display->max_tmds_clock = max_tmds_clock;
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DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
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display->max_tmds_clock);
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}
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if (scdc->supported) {
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scdc->scrambling.supported = true;
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/* Few sinks support scrambling for cloks < 340M */
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if ((hf_vsdb[6] & 0x8))
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scdc->scrambling.low_rates = true;
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}
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}
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}
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static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
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@ -22,8 +22,10 @@
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*/
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <drm/drm_scdc_helper.h>
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#include <drm/drmP.h>
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/**
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* DOC: scdc helpers
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@ -121,3 +123,122 @@ ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
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return 0;
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}
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EXPORT_SYMBOL(drm_scdc_write);
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/**
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* drm_scdc_check_scrambling_status - what is status of scrambling?
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* @adapter: I2C adapter for DDC channel
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*
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* Reads the scrambler status over SCDC, and checks the
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* scrambling status.
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*
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* Returns:
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* True if the scrambling is enabled, false otherwise.
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*/
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bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter)
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{
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u8 status;
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int ret;
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ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status);
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if (ret < 0) {
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DRM_ERROR("Failed to read scrambling status, error %d\n", ret);
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return false;
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}
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return status & SCDC_SCRAMBLING_STATUS;
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}
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EXPORT_SYMBOL(drm_scdc_get_scrambling_status);
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/**
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* drm_scdc_set_scrambling - enable scrambling
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* @adapter: I2C adapter for DDC channel
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* @enable: bool to indicate if scrambling is to be enabled/disabled
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*
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* Writes the TMDS config register over SCDC channel, and:
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* enables scrambling when enable = 1
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* disables scrambling when enable = 0
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*
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* Returns:
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* True if scrambling is set/reset successfully, false otherwise.
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*/
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bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable)
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{
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u8 config;
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int ret;
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ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
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if (ret < 0) {
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DRM_ERROR("Failed to read tmds config, err=%d\n", ret);
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return false;
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}
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if (enable)
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config |= SCDC_SCRAMBLING_ENABLE;
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else
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config &= ~SCDC_SCRAMBLING_ENABLE;
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ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
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if (ret < 0) {
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DRM_ERROR("Failed to enable scrambling, error %d\n", ret);
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return false;
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}
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return true;
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}
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EXPORT_SYMBOL(drm_scdc_set_scrambling);
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/**
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* drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
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* @adapter: I2C adapter for DDC channel
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* @set: ret or reset the high clock ratio
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*
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* TMDS clock ratio calculations go like this:
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* TMDS character = 10 bit TMDS encoded value
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* TMDS character rate = The rate at which TMDS characters are transmitted(Mcsc)
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* TMDS bit rate = 10x TMDS character rate
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* As per the spec:
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* TMDS clock rate for pixel clock < 340 MHz = 1x the character rate
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* = 1/10 pixel clock rate
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* TMDS clock rate for pixel clock > 340 MHz = 0.25x the character rate
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* = 1/40 pixel clock rate
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*
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* Writes to the TMDS config register over SCDC channel, and:
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* sets TMDS clock ratio to 1/40 when set = 1
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* sets TMDS clock ratio to 1/10 when set = 0
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*
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* Returns:
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* True if write is successful, false otherwise.
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*/
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bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set)
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{
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u8 config;
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int ret;
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ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
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if (ret < 0) {
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DRM_ERROR("Failed to read tmds config, err=%d\n", ret);
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return false;
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}
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if (set)
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config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
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else
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config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
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ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
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if (ret < 0) {
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DRM_ERROR("Failed to set TMDS clock ratio, error %d\n", ret);
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return false;
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}
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/*
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* The spec says that a source should wait minimum 1ms and maximum
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* 100ms after writing the TMDS config for clock ratio. Lets allow a
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* wait of upto 2ms here.
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*/
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usleep_range(1000, 2000);
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return true;
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}
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EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio);
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@ -90,6 +90,20 @@ enum subpixel_order {
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};
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/**
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* struct drm_scrambling: sink's scrambling support.
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*/
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struct drm_scrambling {
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/**
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* @supported: scrambling supported for rates > 340 Mhz.
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*/
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bool supported;
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/**
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* @low_rates: scrambling supported for rates <= 340 Mhz.
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*/
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bool low_rates;
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};
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/*
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* struct drm_scdc - Information about scdc capabilities of a HDMI 2.0 sink
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*
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* @read_request: sink is capable of generating scdc read request.
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*/
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bool read_request;
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/**
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* @scrambling: sink's scrambling capabilities
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*/
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struct drm_scrambling scrambling;
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};
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/**
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* struct drm_hdmi_info - runtime information about the connected HDMI sink
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*
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@ -476,5 +476,4 @@ void drm_edid_get_monitor_name(struct edid *edid, char *name,
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struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
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int hsize, int vsize, int fresh,
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bool rb);
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#endif /* __DRM_EDID_H__ */
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@ -129,4 +129,31 @@ static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset,
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return drm_scdc_write(adapter, offset, &value, sizeof(value));
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}
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/**
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* drm_scdc_set_scrambling - enable scrambling
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* @adapter: I2C adapter for DDC channel
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* @enable: bool to indicate if scrambling is to be enabled/disabled
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*
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* Writes the TMDS config register over SCDC channel, and:
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* enables scrambling when enable = 1
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* disables scrambling when enable = 0
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*
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* Returns:
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* True if scrambling is set/reset successfully, false otherwise.
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*/
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bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable);
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/**
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* drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
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* @adapter: I2C adapter for DDC channel
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* @set: ret or reset the high clock ratio
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*
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* Writes to the TMDS config register over SCDC channel, and:
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* sets TMDS clock ratio to 1/40 when set = 1
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* sets TMDS clock ratio to 1/10 when set = 0
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*
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* Returns:
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* True if write is successful, false otherwise.
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*/
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bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set);
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#endif
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