From 630a6a466b5afff0ec5824e6f62e5dba15812256 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 11 Sep 2014 22:59:13 +1000 Subject: [PATCH] drm/nouveau/pwr/memx: rename fb off/on to block/unblock More accurate as to the function of the opcodes. Not only is FB disabled, but the host is prevented from touching the GPU. An upcoming patch for Kepler will also halt PFIFO (as NVIDIA does). Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/core/include/subdev/pwr.h | 4 ++-- drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h | 12 ++++++------ drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | 8 ++++---- drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc | 4 ++-- drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h | 4 ++-- drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c | 12 ++++++------ 6 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h index 1c4668505970..bf3d1f611333 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h @@ -48,7 +48,7 @@ void nouveau_memx_wait(struct nouveau_memx *, u32 addr, u32 mask, u32 data, u32 nsec); void nouveau_memx_nsec(struct nouveau_memx *, u32 nsec); void nouveau_memx_wait_vblank(struct nouveau_memx *); -void nouveau_memx_fb_disable(struct nouveau_memx *); -void nouveau_memx_fb_enable(struct nouveau_memx *); +void nouveau_memx_block(struct nouveau_memx *); +void nouveau_memx_unblock(struct nouveau_memx *); #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h index 430261a307a4..6ae560accb1f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h @@ -112,15 +112,15 @@ ramfuc_wait_vblank(struct ramfuc *ram) } static inline void -ramfuc_fb_disable(struct ramfuc *ram) +ramfuc_block(struct ramfuc *ram) { - nouveau_memx_fb_disable(ram->memx); + nouveau_memx_block(ram->memx); } static inline void -ramfuc_fb_enable(struct ramfuc *ram) +ramfuc_unblock(struct ramfuc *ram) { - nouveau_memx_fb_enable(ram->memx); + nouveau_memx_unblock(ram->memx); } #define ram_init(s,p) ramfuc_init(&(s)->base, (p)) @@ -133,7 +133,7 @@ ramfuc_fb_enable(struct ramfuc *ram) #define ram_wait(s,r,m,d,n) ramfuc_wait(&(s)->base, (r), (m), (d), (n)) #define ram_nsec(s,n) ramfuc_nsec(&(s)->base, (n)) #define ram_wait_vblank(s) ramfuc_wait_vblank(&(s)->base) -#define ram_fb_disable(s) ramfuc_fb_disable(&(s)->base) -#define ram_fb_enable(s) ramfuc_fb_enable(&(s)->base) +#define ram_block(s) ramfuc_block(&(s)->base) +#define ram_unblock(s) ramfuc_unblock(&(s)->base) #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c index 8fda31a33ad9..66d8abb1475b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c @@ -264,7 +264,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) u32 mask, data; ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); - ram_fb_disable(fuc); + ram_block(fuc); ram_wr32(fuc, 0x62c000, 0x0f0f0000); /* MR1: turn termination on early, for some reason.. */ @@ -663,7 +663,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) if (next->bios.ramcfg_11_07_02) nve0_ram_train(fuc, 0x80020000, 0x01000000); - ram_fb_enable(fuc); + ram_unblock(fuc); ram_wr32(fuc, 0x62c000, 0x0f0f0f00); if (next->bios.rammap_11_08_01) @@ -693,7 +693,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) u32 mask, data; ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); - ram_fb_disable(fuc); + ram_block(fuc); ram_wr32(fuc, 0x62c000, 0x0f0f0000); if (vc == 1 && ram_have(fuc, gpio2E)) { @@ -916,7 +916,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); ram_nsec(fuc, 1000); - ram_fb_enable(fuc); + ram_unblock(fuc); ram_wr32(fuc, 0x62c000, 0x0f0f0f00); if (next->bios.rammap_11_08_01) diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc index 744f2e9d492d..635539700216 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc @@ -43,9 +43,9 @@ process(PROC_MEMX, #memx_init, #memx_recv) */ .b32 func memx_func_head: -handler(FB_OFF, 0x0000, 0x0000, #memx_func_enter) +handler(ENTER , 0x0000, 0x0000, #memx_func_enter) memx_func_next: -handler(FB_ON , 0x0000, 0x0000, #memx_func_leave) +handler(LEAVE , 0x0000, 0x0000, #memx_func_leave) handler(WR32 , 0x0000, 0x0002, #memx_func_wr32) handler(WAIT , 0x0004, 0x0000, #memx_func_wait) handler(DELAY , 0x0001, 0x0000, #memx_func_delay) diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h index 50f9a38a0924..80f8328fa6da 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h @@ -19,8 +19,8 @@ #define MEMX_MSG_EXEC 1 /* MEMX: script opcode definitions */ -#define MEMX_FB_OFF 0 -#define MEMX_FB_ON 1 +#define MEMX_ENTER 0 +#define MEMX_LEAVE 1 #define MEMX_WR32 2 #define MEMX_WAIT 3 #define MEMX_DELAY 4 diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c index 8edd411426dd..ea57491ab58d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c @@ -151,21 +151,21 @@ nouveau_memx_wait_vblank(struct nouveau_memx *memx) } void -nouveau_memx_fb_disable(struct nouveau_memx *memx) +nouveau_memx_block(struct nouveau_memx *memx) { struct nouveau_pwr *ppwr = memx->ppwr; - nv_debug(memx->ppwr, " FB OFF\n"); - nv_wr32(ppwr, 0x10a1c4, MEMX_FB_OFF); + nv_debug(memx->ppwr, " HOST BLOCKED\n"); + nv_wr32(ppwr, 0x10a1c4, MEMX_ENTER); } void -nouveau_memx_fb_enable(struct nouveau_memx *memx) +nouveau_memx_unblock(struct nouveau_memx *memx) { struct nouveau_pwr *ppwr = memx->ppwr; - nv_debug(memx->ppwr, " FB ON\n"); - nv_wr32(ppwr, 0x10a1c4, MEMX_FB_ON); + nv_debug(memx->ppwr, " HOST UNBLOCKED\n"); + nv_wr32(ppwr, 0x10a1c4, MEMX_LEAVE); } #endif