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ARM: dts: meson: provide the XTAL clock using a fixed-clock

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The clock controller driver has provided the XTAL clock so far. This
does not match how the hardware actually works because the XTAL clock is
an actual crystal which is mounted on the PCB.

Add the "xtal" clock to meson.dtsi and replace all references to the
clock controller's CLKID_XTAL with the new xtal clock node.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Martin Blumenstingl 2019-12-08 19:05:23 +01:00 committed by Kevin Hilman
parent 9cf7956865
commit 630ea3108a
7 changed files with 26 additions and 24 deletions
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7
arch/arm/boot/dts/meson.dtsi
View file

@ -282,4 +282,11 @@
};
};
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
}; /* end of / */

7
arch/arm/boot/dts/meson6.dtsi
View file

@ -36,13 +36,6 @@
ranges = <0x0 0xd0000000 0x40000>;
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
clk81: clk@0 {
#clock-cells = <0>;
compatible = "fixed-clock";

15
arch/arm/boot/dts/meson8.dtsi
View file

@ -455,6 +455,8 @@
&hhi {
clkc: clock-controller {
compatible = "amlogic,meson8-clkc";
clocks = <&xtal>;
clock-names = "xtal";
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -529,8 +531,7 @@
&saradc {
compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
clocks = <&clkc CLKID_XTAL>,
<&clkc CLKID_SAR_ADC>;
clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
clock-names = "clkin", "core";
amlogic,hhi-sysctrl = <&hhi>;
nvmem-cells = <&temperature_calib>;
@ -548,31 +549,31 @@
};
&timer_abcde {
clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "pclk";
};
&uart_AO {
compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "baud", "xtal", "pclk";
};
&uart_A {
compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
clock-names = "baud", "xtal", "pclk";
};
&uart_B {
compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
clock-names = "baud", "xtal", "pclk";
};
&uart_C {
compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
clock-names = "baud", "xtal", "pclk";
};

2
arch/arm/boot/dts/meson8b-ec100.dts
View file

@ -377,7 +377,7 @@
status = "okay";
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
clocks = <&xtal>, <&xtal>;
clock-names = "clkin0", "clkin1";
};

2
arch/arm/boot/dts/meson8b-mxq.dts
View file

@ -165,7 +165,7 @@
status = "okay";
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
clocks = <&xtal>, <&xtal>;
clock-names = "clkin0", "clkin1";
};

2
arch/arm/boot/dts/meson8b-odroidc1.dts
View file

@ -340,7 +340,7 @@
status = "okay";
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
clocks = <&xtal>, <&xtal>;
clock-names = "clkin0", "clkin1";
};

15
arch/arm/boot/dts/meson8b.dtsi
View file

@ -434,6 +434,8 @@
&hhi {
clkc: clock-controller {
compatible = "amlogic,meson8-clkc";
clocks = <&xtal>;
clock-names = "xtal";
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -508,8 +510,7 @@
&saradc {
compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
clocks = <&clkc CLKID_XTAL>,
<&clkc CLKID_SAR_ADC>;
clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
clock-names = "clkin", "core";
amlogic,hhi-sysctrl = <&hhi>;
nvmem-cells = <&temperature_calib>;
@ -523,31 +524,31 @@
};
&timer_abcde {
clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "pclk";
};
&uart_AO {
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "baud", "xtal", "pclk";
};
&uart_A {
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
clock-names = "baud", "xtal", "pclk";
};
&uart_B {
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
clock-names = "baud", "xtal", "pclk";
};
&uart_C {
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
clock-names = "baud", "xtal", "pclk";
};