irqchip/qeic: remove PPCisms for QEIC
QEIC was supported on PowerPC, and dependent on PPC, Now it is supported on other platforms, so remove PPCisms. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>5.4-rM2-2.2.x-imx-squashed
parent
2fc190c911
commit
6318feef83
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@ -14,7 +14,11 @@
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#include <linux/of_address.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/errno.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/reboot.h>
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#include <linux/slab.h>
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#include <linux/stddef.h>
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@ -22,9 +26,8 @@
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#include <linux/signal.h>
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#include <linux/device.h>
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#include <linux/spinlock.h>
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#include <asm/irq.h>
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <soc/fsl/qe/qe_ic.h>
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#define NR_QE_IC_INTS 64
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@ -82,6 +85,43 @@
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#define SIGNAL_HIGH 2
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#define SIGNAL_LOW 0
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#define NUM_OF_QE_IC_GROUPS 6
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/* Flags when we init the QE IC */
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#define QE_IC_SPREADMODE_GRP_W 0x00000001
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#define QE_IC_SPREADMODE_GRP_X 0x00000002
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#define QE_IC_SPREADMODE_GRP_Y 0x00000004
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#define QE_IC_SPREADMODE_GRP_Z 0x00000008
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#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
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#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
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#define QE_IC_LOW_SIGNAL 0x00000100
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#define QE_IC_HIGH_SIGNAL 0x00000200
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#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
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#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
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#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
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#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
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#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
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#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
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#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
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#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
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#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
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#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
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#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
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#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
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#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
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/* QE interrupt sources groups */
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enum qe_ic_grp_id {
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QE_IC_GRP_W = 0, /* QE interrupt controller group W */
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QE_IC_GRP_X, /* QE interrupt controller group X */
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QE_IC_GRP_Y, /* QE interrupt controller group Y */
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QE_IC_GRP_Z, /* QE interrupt controller group Z */
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QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
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QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
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};
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struct qe_ic {
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/* Control registers offset */
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u32 __iomem *regs;
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@ -260,15 +300,15 @@ static struct qe_ic_info qe_ic_info[] = {
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},
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};
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static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
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static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
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{
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return in_be32(base + (reg >> 2));
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return ioread32be(base + (reg >> 2));
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}
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static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
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static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
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u32 value)
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{
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out_be32(base + (reg >> 2), value);
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iowrite32be(value, base + (reg >> 2));
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}
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static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
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@ -370,8 +410,8 @@ static const struct irq_domain_ops qe_ic_host_ops = {
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.xlate = irq_domain_xlate_onetwocell,
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};
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/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
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unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
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/* Return an interrupt vector or 0 if no interrupt is pending. */
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static unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
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{
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int irq;
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@ -381,13 +421,13 @@ unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
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irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
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if (irq == 0)
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return NO_IRQ;
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return 0;
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return irq_linear_revmap(qe_ic->irqhost, irq);
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}
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/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
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unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
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/* Return an interrupt vector or 0 if no interrupt is pending. */
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static unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
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{
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int irq;
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@ -397,11 +437,69 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
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irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
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if (irq == 0)
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return NO_IRQ;
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return 0;
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return irq_linear_revmap(qe_ic->irqhost, irq);
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}
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static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
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if (cascade_irq != 0)
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generic_handle_irq(cascade_irq);
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}
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static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
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if (cascade_irq != 0)
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generic_handle_irq(cascade_irq);
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}
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static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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if (cascade_irq != 0)
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generic_handle_irq(cascade_irq);
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chip->irq_eoi(&desc->irq_data);
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}
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static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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if (cascade_irq != 0)
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generic_handle_irq(cascade_irq);
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chip->irq_eoi(&desc->irq_data);
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}
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static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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cascade_irq = qe_ic_get_high_irq(qe_ic);
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if (cascade_irq == 0)
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cascade_irq = qe_ic_get_low_irq(qe_ic);
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if (cascade_irq != 0)
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generic_handle_irq(cascade_irq);
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chip->irq_eoi(&desc->irq_data);
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}
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static int __init qe_ic_init(struct device_node *node, unsigned int flags)
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{
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struct qe_ic *qe_ic;
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@ -438,7 +536,7 @@ static int __init qe_ic_init(struct device_node *node, unsigned int flags)
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qe_ic->virq_high = irq_of_parse_and_map(node, 0);
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qe_ic->virq_low = irq_of_parse_and_map(node, 1);
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if (qe_ic->virq_low == NO_IRQ) {
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if (qe_ic->virq_low == 0) {
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pr_err("Failed to map QE_IC low IRQ\n");
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ret = -ENOMEM;
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goto err_domain_remove;
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@ -470,7 +568,7 @@ static int __init qe_ic_init(struct device_node *node, unsigned int flags)
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irq_set_handler_data(qe_ic->virq_low, qe_ic);
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irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
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if (qe_ic->virq_high != NO_IRQ &&
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if (qe_ic->virq_high != 0 &&
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qe_ic->virq_high != qe_ic->virq_low) {
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irq_set_handler_data(qe_ic->virq_high, qe_ic);
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irq_set_chained_handler(qe_ic->virq_high,
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@ -488,100 +586,6 @@ err_put_node:
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return ret;
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}
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void qe_ic_set_highest_priority(unsigned int virq, int high)
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{
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struct qe_ic *qe_ic = qe_ic_from_irq(virq);
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unsigned int src = virq_to_hw(virq);
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u32 temp = 0;
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temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
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temp &= ~CICR_HP_MASK;
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temp |= src << CICR_HP_SHIFT;
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temp &= ~CICR_HPIT_MASK;
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temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
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qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
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}
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/* Set Priority level within its group, from 1 to 8 */
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int qe_ic_set_priority(unsigned int virq, unsigned int priority)
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{
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struct qe_ic *qe_ic = qe_ic_from_irq(virq);
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unsigned int src = virq_to_hw(virq);
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u32 temp;
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if (priority > 8 || priority == 0)
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return -EINVAL;
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if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
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"%s: Invalid hw irq number for QEIC\n", __func__))
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return -EINVAL;
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if (qe_ic_info[src].pri_reg == 0)
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return -EINVAL;
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temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
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if (priority < 4) {
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temp &= ~(0x7 << (32 - priority * 3));
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temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
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} else {
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temp &= ~(0x7 << (24 - priority * 3));
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temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
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}
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qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
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return 0;
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}
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/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
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int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
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{
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struct qe_ic *qe_ic = qe_ic_from_irq(virq);
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unsigned int src = virq_to_hw(virq);
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u32 temp, control_reg = QEIC_CICNR, shift = 0;
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if (priority > 2 || priority == 0)
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return -EINVAL;
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if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
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"%s: Invalid hw irq number for QEIC\n", __func__))
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return -EINVAL;
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switch (qe_ic_info[src].pri_reg) {
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case QEIC_CIPZCC:
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shift = CICNR_ZCC1T_SHIFT;
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break;
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case QEIC_CIPWCC:
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shift = CICNR_WCC1T_SHIFT;
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break;
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case QEIC_CIPYCC:
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shift = CICNR_YCC1T_SHIFT;
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break;
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case QEIC_CIPXCC:
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shift = CICNR_XCC1T_SHIFT;
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break;
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case QEIC_CIPRTA:
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shift = CRICR_RTA1T_SHIFT;
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control_reg = QEIC_CRICR;
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break;
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case QEIC_CIPRTB:
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shift = CRICR_RTB1T_SHIFT;
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control_reg = QEIC_CRICR;
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break;
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default:
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return -EINVAL;
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}
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shift += (2 - priority) * 2;
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temp = qe_ic_read(qe_ic->regs, control_reg);
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temp &= ~(SIGNAL_MASK << shift);
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temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
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qe_ic_write(qe_ic->regs, control_reg, temp);
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return 0;
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}
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static int __init init_qe_ic(struct device_node *node,
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struct device_node *parent)
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{
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@ -1,128 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Authors: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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*
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* Description:
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* QE IC external definitions and structure.
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*/
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#ifndef _ASM_POWERPC_QE_IC_H
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#define _ASM_POWERPC_QE_IC_H
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#include <linux/irq.h>
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struct device_node;
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struct qe_ic;
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#define NUM_OF_QE_IC_GROUPS 6
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/* Flags when we init the QE IC */
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#define QE_IC_SPREADMODE_GRP_W 0x00000001
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#define QE_IC_SPREADMODE_GRP_X 0x00000002
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#define QE_IC_SPREADMODE_GRP_Y 0x00000004
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#define QE_IC_SPREADMODE_GRP_Z 0x00000008
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#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
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#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
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#define QE_IC_LOW_SIGNAL 0x00000100
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#define QE_IC_HIGH_SIGNAL 0x00000200
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#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
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#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
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#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
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#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
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#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
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#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
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#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
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#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
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#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
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#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
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#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
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#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
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#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
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/* QE interrupt sources groups */
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enum qe_ic_grp_id {
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QE_IC_GRP_W = 0, /* QE interrupt controller group W */
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QE_IC_GRP_X, /* QE interrupt controller group X */
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QE_IC_GRP_Y, /* QE interrupt controller group Y */
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QE_IC_GRP_Z, /* QE interrupt controller group Z */
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QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
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QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
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};
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#ifdef CONFIG_QUICC_ENGINE
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unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
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unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
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#else
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static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
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{ return 0; }
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static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
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{ return 0; }
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#endif /* CONFIG_QUICC_ENGINE */
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void qe_ic_set_highest_priority(unsigned int virq, int high);
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int qe_ic_set_priority(unsigned int virq, unsigned int priority);
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int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
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static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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}
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static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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}
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static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
|
||||
{
|
||||
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
|
||||
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
|
||||
if (cascade_irq != NO_IRQ)
|
||||
generic_handle_irq(cascade_irq);
|
||||
|
||||
chip->irq_eoi(&desc->irq_data);
|
||||
}
|
||||
|
||||
static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
|
||||
{
|
||||
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
|
||||
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
|
||||
if (cascade_irq != NO_IRQ)
|
||||
generic_handle_irq(cascade_irq);
|
||||
|
||||
chip->irq_eoi(&desc->irq_data);
|
||||
}
|
||||
|
||||
static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
|
||||
{
|
||||
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
|
||||
unsigned int cascade_irq;
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
|
||||
cascade_irq = qe_ic_get_high_irq(qe_ic);
|
||||
if (cascade_irq == NO_IRQ)
|
||||
cascade_irq = qe_ic_get_low_irq(qe_ic);
|
||||
|
||||
if (cascade_irq != NO_IRQ)
|
||||
generic_handle_irq(cascade_irq);
|
||||
|
||||
chip->irq_eoi(&desc->irq_data);
|
||||
}
|
||||
|
||||
#endif /* _ASM_POWERPC_QE_IC_H */
|
Loading…
Reference in New Issue