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clk: iproc: Fix PLL output frequency calculation 

This patch affects the clocks that use fractional ndivider in their
PLL output frequency calculation. Instead of 2^20 divide factor, the
clock's ndiv integer shift was used. Fixed the bug by replacing ndiv
integer shift with 2^20 factor.

Signed-off-by: Simran Rai <ssimran@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Fixes: 5fe225c105 ("clk: iproc: add initial common clock support")
Cc: <stable@vger.kernel.org> # v4.1+
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
hifive-unleashed-5.1
Simran Rai 2015-10-19 15:27:19 -07:00 committed by Michael Turquette
parent 1256f10fb2
commit 63243a4da7
1 changed files with 5 additions and 8 deletions
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13
drivers/clk/bcm/clk-iproc-pll.c
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@ -345,8 +345,8 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
struct iproc_pll *pll = clk->pll;
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
u32 val;
u64 ndiv;
unsigned int ndiv_int, ndiv_frac, pdiv;
u64 ndiv, ndiv_int, ndiv_frac;
unsigned int pdiv;
if (parent_rate == 0)
return 0;
@ -366,22 +366,19 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
val = readl(pll->pll_base + ctrl->ndiv_int.offset);
ndiv_int = (val >> ctrl->ndiv_int.shift) &
bit_mask(ctrl->ndiv_int.width);
ndiv = (u64)ndiv_int << ctrl->ndiv_int.shift;
ndiv = ndiv_int << 20;
if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
ndiv_frac = (val >> ctrl->ndiv_frac.shift) &
bit_mask(ctrl->ndiv_frac.width);
if (ndiv_frac != 0)
ndiv = ((u64)ndiv_int << ctrl->ndiv_int.shift) |
ndiv_frac;
ndiv += ndiv_frac;
}
val = readl(pll->pll_base + ctrl->pdiv.offset);
pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width);
clk->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift;
clk->rate = (ndiv * parent_rate) >> 20;
if (pdiv == 0)
clk->rate *= 2;