drm/i915: Correctly prefix HSW/BDW HDMI clock functions
Those functions were the only one in existence when they were introduced. We now know they are only valid for HSW/BDW. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -625,11 +625,11 @@ intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
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(void) (&__a == &__b); \
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(void) (&__a == &__b); \
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__a > __b ? (__a - __b) : (__b - __a); })
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__a > __b ? (__a - __b) : (__b - __a); })
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struct wrpll_rnp {
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struct hsw_wrpll_rnp {
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unsigned p, n2, r2;
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unsigned p, n2, r2;
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};
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};
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static unsigned wrpll_get_budget_for_freq(int clock)
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static unsigned hsw_wrpll_get_budget_for_freq(int clock)
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{
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{
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unsigned budget;
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unsigned budget;
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@ -703,9 +703,9 @@ static unsigned wrpll_get_budget_for_freq(int clock)
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return budget;
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return budget;
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}
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}
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static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
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static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
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unsigned r2, unsigned n2, unsigned p,
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unsigned r2, unsigned n2, unsigned p,
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struct wrpll_rnp *best)
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struct hsw_wrpll_rnp *best)
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{
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{
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uint64_t a, b, c, d, diff, diff_best;
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uint64_t a, b, c, d, diff, diff_best;
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@ -762,8 +762,7 @@ static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
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/* Otherwise a < c && b >= d, do nothing */
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/* Otherwise a < c && b >= d, do nothing */
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}
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}
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static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
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static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
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int reg)
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{
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{
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int refclk = LC_FREQ;
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int refclk = LC_FREQ;
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int n, p, r;
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int n, p, r;
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@ -929,10 +928,10 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
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link_clock = 270000;
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link_clock = 270000;
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break;
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break;
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case PORT_CLK_SEL_WRPLL1:
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case PORT_CLK_SEL_WRPLL1:
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link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
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link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
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break;
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break;
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case PORT_CLK_SEL_WRPLL2:
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case PORT_CLK_SEL_WRPLL2:
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link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
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link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
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break;
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break;
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case PORT_CLK_SEL_SPLL:
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case PORT_CLK_SEL_SPLL:
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pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
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pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
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@ -1011,12 +1010,12 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
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{
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{
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uint64_t freq2k;
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uint64_t freq2k;
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unsigned p, n2, r2;
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unsigned p, n2, r2;
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struct wrpll_rnp best = { 0, 0, 0 };
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struct hsw_wrpll_rnp best = { 0, 0, 0 };
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unsigned budget;
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unsigned budget;
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freq2k = clock / 100;
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freq2k = clock / 100;
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budget = wrpll_get_budget_for_freq(clock);
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budget = hsw_wrpll_get_budget_for_freq(clock);
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/* Special case handling for 540 pixel clock: bypass WR PLL entirely
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/* Special case handling for 540 pixel clock: bypass WR PLL entirely
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* and directly pass the LC PLL to it. */
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* and directly pass the LC PLL to it. */
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@ -1060,8 +1059,8 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
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n2++) {
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n2++) {
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for (p = P_MIN; p <= P_MAX; p += P_INC)
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for (p = P_MIN; p <= P_MAX; p += P_INC)
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wrpll_update_rnp(freq2k, budget,
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hsw_wrpll_update_rnp(freq2k, budget,
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r2, n2, p, &best);
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r2, n2, p, &best);
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}
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}
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}
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}
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