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spi: sh-msiof: Reduce delays in sh_msiof_modify_ctr_wait() 

While the Hardware User Manual does not document the maximum time needed
for modifying bits in the MSIOF Control Register, experiments on R-Car
Gen2/Gen3 and SH-Mobile AG5 revealed the following typical modification
times for the various bits:
  - CTR.TXE and CTR.RXE: no delay,
  - CTR.TSCKE: less than 10 ns,
  - CTR.TFSE: up to a few hundred ns (depending on SPI transfer clock,
    i.e. less for faster transfers).
There are no reasons to believe these figures are different for
SH-MobileR2 SoCs (SH7723/SH7724).

Hence the minimum busy-looping delay of 10 µs is excessive.
Reduce the delay per loop iteration from 10 to 1 us, and the maximum
delay from 1000 to 100 µs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mark Brown <broonie@kernel.org>
alistair/sunxi64-5.4-dsi
Geert Uytterhoeven 2019-05-27 14:19:35 +02:00 committed by Mark Brown
parent d9424d6d48
commit 635bdb7a3e
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GPG Key ID: 24D68B725D5487D0
1 changed files with 1 additions and 1 deletions
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drivers/spi/spi-sh-msiof.c
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@ -229,7 +229,7 @@ static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
sh_msiof_write(p, CTR, data);
return readl_poll_timeout_atomic(p->mapbase + CTR, data,
(data & mask) == set, 10, 1000);
(data & mask) == set, 1, 100);
}
static irqreturn_t sh_msiof_spi_irq(int irq, void *data)