Renesas ARM64 Based SoC DT Updates for v4.5
* Initial support for Renesas ARM64 Based r8a7795 SoC and Salvator-X board -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWTm0oAAoJENfPZGlqN0++n8EP/1Xg9Yx1KzY5Ss2yLviTFy7k 1L0UpgYotdahDZr3x0QAeXNSEzJOyxjau9eg9+gwbuDxIYZNt8jO3tfAXzqcbNkv 0X7m3BL7K5f1EOWEpaOq4pwdSkKTjPs3CycjS3lYJtI9WQj0lmsBVTuuF77CuZjr aZa432UCzdnZEs9B/YA4HkOVb3s1Y5pLeiD28NPDK/ZJE1lR0+of2sVgK1YuteXx pff13nOuOaYuU5mdkbhmE1Djkl6O4UTo8bJcK9ylzoht2dj672ftJuVA5bp5jox6 I3O+x4NPoByGEGQ7cdg4kihqEbAcVEWm6GaXk6/3Kq+1KKafELY6F0ABsHmOANFk fjtq9PQjFPYO/ygrxN/4pDvr7u6WCOFWEk/SgfJKg1dVPZN54K0kcr5P1gggzDx8 pgRg0h0Rnf4uSZCAtVmLMcoFWOb3ZKzHbmv5rUxgVXovMJiSBQrMQyfMnn/t+uVf PrTzJDR9/FodmvmJ2oKPkLuiH8MOUFaUiP91A2Se68ijCglIXZ65j6rGBZtsrrkQ hGIYu8HL43AWsAqVzrFQIFmT9cqQh728o3ahJtHn/XkqHmuO2D1Z8/MzdHnFybyy FCuma2pROhFfbj4T/dgd2IWFC3SgTVSP2HI5VLsdJ4uyEIEqjxCErc22rzawGB9C XK0fRUn6cy7jntdeKMN3 =MVJ0 -----END PGP SIGNATURE----- Merge tag 'renesas-arm64-dt-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64 Merge "Renesas ARM64 Based SoC DT Updates for v4.5" from Simon Horman: * Initial support for Renesas ARM64 Based r8a7795 SoC and Salvator-X board * tag 'renesas-arm64-dt-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: MAINTAINERS: Add entry for Renesas arm64 architecture arm64: renesas: add Salvator-X board support arm64: renesas: r8a7795: enable PFC arm64: renesas: r8a7795: Add all SCIF nodes arm64: renesas: r8a7795: Add dummy dma-controller nodes arm64: renesas: r8a7795: Add Renesas R8A7795 SoC supporthifive-unleashed-5.1
Arnd Bergmann
commit
63747d3c27
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@ -27,6 +27,8 @@ SoCs:
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compatible = "renesas,r8a7793"
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- R-Car E2 (R8A77940)
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compatible = "renesas,r8a7794"
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- R-Car H3 (R8A77950)
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compatible = "renesas,r8a7795"
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Boards:
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@ -57,5 +59,7 @@ Boards:
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compatible = "renesas,marzen", "renesas,r8a7779"
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- Porter (M2-LCDP)
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compatible = "renesas,porter", "renesas,r8a7791"
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- Salvator-X
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compatible = "renesas,salvator-x", "renesas,r8a7795";
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- SILK (RTP0RC7794LCB00011S)
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compatible = "renesas,silk", "renesas,r8a7794"
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@ -1420,6 +1420,15 @@ M: Lennert Buytenhek <kernel@wantstofly.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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ARM/RENESAS ARM64 ARCHITECTURE
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M: Simon Horman <horms@verge.net.au>
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M: Magnus Damm <magnus.damm@gmail.com>
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L: linux-sh@vger.kernel.org
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Q: http://patchwork.kernel.org/project/linux-sh/list/
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
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S: Supported
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F: arch/arm64/boot/dts/renesas/
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ARM/RISCPC ARCHITECTURE
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M: Russell King <linux@arm.linux.org.uk>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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@ -67,6 +67,23 @@ config ARCH_SEATTLE
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help
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This enables support for AMD Seattle SOC Family
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config ARCH_SHMOBILE
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bool
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config ARCH_RENESAS
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bool "Renesas SoC Platforms"
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select ARCH_SHMOBILE
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select PINCTRL
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select PM_GENERIC_DOMAINS if PM
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help
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This enables support for the ARMv8 based Renesas SoCs.
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config ARCH_R8A7795
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bool "Renesas R-Car H3 SoC Platform"
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depends on ARCH_RENESAS
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help
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This enables support for the Renesas R-Car H3 SoC.
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config ARCH_STRATIX10
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bool "Altera's Stratix 10 SoCFPGA Family"
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help
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@ -10,6 +10,7 @@ dts-dirs += hisilicon
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dts-dirs += marvell
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dts-dirs += mediatek
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dts-dirs += qcom
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dts-dirs += renesas
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dts-dirs += rockchip
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dts-dirs += sprd
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dts-dirs += xilinx
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@ -0,0 +1,4 @@
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dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb
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always := $(dtb-y)
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clean-files := *.dtb
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@ -0,0 +1,62 @@
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/*
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* Device Tree Source for the Salvator-X board
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*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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#include "r8a7795.dtsi"
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/ {
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model = "Renesas Salvator-X board based on r8a7795";
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compatible = "renesas,salvator-x", "renesas,r8a7795";
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aliases {
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serial0 = &scif2;
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serial1 = &scif1;
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};
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chosen {
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bootargs = "ignore_loglevel";
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stdout-path = "serial0:115200n8";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x38000000>;
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};
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};
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&extal_clk {
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clock-frequency = <16666666>;
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};
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&pfc {
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scif1_pins: scif1 {
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renesas,groups = "scif1_data_a", "scif1_ctrl";
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renesas,function = "scif1";
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};
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scif2_pins: scif2 {
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renesas,groups = "scif2_data_a";
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renesas,function = "scif2";
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};
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};
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&scif1 {
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pinctrl-0 = <&scif1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&scif2 {
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pinctrl-0 = <&scif2_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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@ -0,0 +1,173 @@
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/*
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* Device Tree Source for the r8a7795 SoC
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*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "renesas,r8a7795";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* 1 core only at this point */
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a57_0: cpu@0 {
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x0>;
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device_type = "cpu";
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@0xf1010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xf1010000 0 0x1000>,
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<0x0 0xf1020000 0 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7795-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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};
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pfc: pfc@e6060000 {
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compatible = "renesas,pfc-r8a7795";
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reg = <0 0xe6060000 0 0x50c>;
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};
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dmac0: dma-controller@e6700000 {
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/* Empty node for now */
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};
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dmac1: dma-controller@e7300000 {
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/* Empty node for now */
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};
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dmac2: dma-controller@e7310000 {
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/* Empty node for now */
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};
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a7795", "renesas,scif";
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reg = <0 0xe6e60000 0 64>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 207>;
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clock-names = "sci_ick";
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dmas = <&dmac1 0x51>, <&dmac1 0x50>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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status = "disabled";
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};
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scif1: serial@e6e68000 {
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compatible = "renesas,scif-r8a7795", "renesas,scif";
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reg = <0 0xe6e68000 0 64>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 206>;
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clock-names = "sci_ick";
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dmas = <&dmac1 0x53>, <&dmac1 0x52>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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status = "disabled";
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};
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scif2: serial@e6e88000 {
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compatible = "renesas,scif-r8a7795", "renesas,scif";
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reg = <0 0xe6e88000 0 64>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 310>;
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clock-names = "sci_ick";
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dmas = <&dmac1 0x13>, <&dmac1 0x12>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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status = "disabled";
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};
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scif3: serial@e6c50000 {
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compatible = "renesas,scif-r8a7795", "renesas,scif";
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reg = <0 0xe6c50000 0 64>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 204>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x57>, <&dmac0 0x56>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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status = "disabled";
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};
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scif4: serial@e6c40000 {
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compatible = "renesas,scif-r8a7795", "renesas,scif";
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reg = <0 0xe6c40000 0 64>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 203>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x59>, <&dmac0 0x58>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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status = "disabled";
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};
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scif5: serial@e6f30000 {
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compatible = "renesas,scif-r8a7795", "renesas,scif";
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reg = <0 0xe6f30000 0 64>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 202>;
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clock-names = "sci_ick";
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dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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status = "disabled";
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};
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};
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};
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