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Renesas ARM Based SoC Lager Board Removal for v3.20 

* Remove legacy r8a7790 SoC and its Lager board code
 * Update serial port names on koelsch and lager boards
 * Remove console bootargs parameter from lager DT
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Merge tag 'renesas-lager-board-removal-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup

Merge "Renesas ARM Based SoC Lager Board Removal for v3.20" from Simon Horman:

"The serial port rename changes are not strictly related to lager board
removal from a feature point of view. But the lager portion of this change
depends on board removal to avoid a regression of booting using that code,
And thus it seems to make sense to put here. And it seems best to put the
koelsch and lager serial port rename changes in the same branch.

Likewise the removal of bootargs from lager DT depends on removing lager
board code to avoid a regression when using it and thus I have included
it in the same branch."

* Remove legacy r8a7790 SoC and its Lager board code
* Update serial port names on koelsch and lager boards
* Remove console bootargs parameter from lager DT

* tag 'renesas-lager-board-removal-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: lager dts: Drop console= bootargs parameter
  ARM: shmobile: koelsch: Rename SCIF[01] serial ports to ttySC[01]
  ARM: shmobile: lager: Rename SCIFA[01] serial ports to ttySC[01]
  ARM: shmobile: r8a7790: Remove legacy code
  ARM: shmobile: lager: Remove legacy board support
  ARM: shmobile: lager-reference: DTS-only board support

Signed-off-by: Olof Johansson <olof@lixom.net>
hifive-unleashed-5.1
Olof Johansson 2015-01-12 14:25:55 -08:00
parent eaa27f34e9 569dd56c99
commit 63bdaa9332
14 changed files with 6 additions and 1818 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -1395,7 +1395,6 @@ F: arch/arm/configs/ape6evm_defconfig
F: arch/arm/configs/armadillo800eva_defconfig
F: arch/arm/configs/bockw_defconfig
F: arch/arm/configs/kzm9g_defconfig
F: arch/arm/configs/lager_defconfig
F: arch/arm/configs/mackerel_defconfig
F: arch/arm/configs/marzen_defconfig
F: arch/arm/configs/shmobile_defconfig

1
arch/arm/boot/dts/Makefile
View File

@ -410,7 +410,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
r8a7778-bockw.dtb \
r8a7778-bockw-reference.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
sh7372-mackerel.dtb \
sh73a0-kzm9g.dtb \
sh73a0-kzm9g-reference.dtb

6
arch/arm/boot/dts/r8a7790-lager.dts
View File

@ -47,12 +47,12 @@
compatible = "renesas,lager", "renesas,r8a7790";
aliases {
serial6 = &scifa0;
serial7 = &scifa1;
serial0 = &scifa0;
serial1 = &scifa1;
};
chosen {
bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = &scifa0;
};

4
arch/arm/boot/dts/r8a7791-koelsch.dts
View File

@ -48,8 +48,8 @@
compatible = "renesas,koelsch", "renesas,r8a7791";
aliases {
serial6 = &scif0;
serial7 = &scif1;
serial0 = &scif0;
serial1 = &scif1;
};
chosen {

150
arch/arm/configs/lager_defconfig
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@ -1,150 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7790=y
CONFIG_MACH_LAGER=y
# CONFIG_SH_TIMER_TMU is not set
# CONFIG_EM_TIMER_STI is not set
CONFIG_ARM_ERRATA_430973=y
CONFIG_ARM_ERRATA_458693=y
CONFIG_ARM_ERRATA_460075=y
CONFIG_ARM_ERRATA_743622=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_PCI=y
CONFIG_PCI_RCAR_GEN2=y
CONFIG_PCI_RCAR_GEN2_PCIE=y
CONFIG_HAVE_ARM_ARCH_TIMER=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_FORCE_MAX_ZONEORDER=13
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_KEXEC=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_VFP=y
CONFIG_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SPI_NOR=y
CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_SATA_RCAR=y
CONFIG_NETDEVICES=y
# CONFIG_NET_CORE is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
CONFIG_SH_ETH=y
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=10
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C_GPIO=y
CONFIG_I2C_SH_MOBILE=y
CONFIG_I2C_RCAR=y
CONFIG_SPI=y
CONFIG_SPI_RSPI=y
CONFIG_SPI_SH_MSIOF=y
CONFIG_GPIO_SH_PFC=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_RCAR=y
# CONFIG_HWMON is not set
CONFIG_THERMAL=y
CONFIG_RCAR_THERMAL=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_DA9210=y
CONFIG_REGULATOR_GPIO=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SOC_CAMERA=y
CONFIG_SOC_CAMERA_PLATFORM=y
CONFIG_VIDEO_RCAR_VIN=y
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_VIDEO_ADV7180=y
CONFIG_DRM=y
CONFIG_DRM_RCAR_DU=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_RCAR=y
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_SDHI=y
CONFIG_MMC_SH_MMCIF=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_DMADEVICES=y
CONFIG_SH_DMAE=y
# CONFIG_IOMMU_SUPPORT is not set
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_ARM_UNWIND is not set
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set

1
arch/arm/configs/shmobile_defconfig
View File

@ -17,7 +17,6 @@ CONFIG_ARCH_R8A7779=y
CONFIG_ARCH_R8A7790=y
CONFIG_ARCH_R8A7791=y
CONFIG_ARCH_R8A7794=y
CONFIG_MACH_LAGER=y
CONFIG_MACH_MARZEN=y
# CONFIG_SWP_EMULATE is not set
CONFIG_CPU_BPREDICT_DISABLE=y

20
arch/arm/mach-shmobile/Kconfig
View File

@ -74,11 +74,6 @@ config ARCH_R8A7794
comment "Renesas ARM SoCs Board Type"
config MACH_LAGER
bool "Lager board"
depends on ARCH_R8A7790
select MICREL_PHY if SH_ETH
config MACH_MARZEN
bool "MARZEN board"
depends on ARCH_R8A7779
@ -133,14 +128,6 @@ config ARCH_R8A7779
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
config ARCH_R8A7790
bool "R-Car H2 (R8A77900)"
select ARCH_RCAR_GEN2
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
select MIGHT_HAVE_PCI
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
comment "Renesas ARM SoCs Board Type"
config MACH_APE6EVM
@ -208,13 +195,6 @@ config MACH_MARZEN
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select USE_OF
config MACH_LAGER
bool "Lager board"
depends on ARCH_R8A7790
select USE_OF
select MICREL_PHY if SH_ETH
select SND_SOC_AK4642 if SND_SIMPLE_CARD
config MACH_KZM9G
bool "KZM-A9-GT board"
depends on ARCH_SH73A0

3
arch/arm/mach-shmobile/Makefile
View File

@ -27,7 +27,6 @@ obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o
obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o
obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
endif
# CPU reset vector handling objects
@ -57,7 +56,6 @@ obj-$(CONFIG_ARCH_SH7372) += entry-intc.o sleep-sh7372.o
# Board objects
ifdef CONFIG_ARCH_SHMOBILE_MULTI
obj-$(CONFIG_MACH_LAGER) += board-lager-reference.o
obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o
else
obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o
@ -66,7 +64,6 @@ obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
obj-$(CONFIG_MACH_LAGER) += board-lager.o
obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o

1
arch/arm/mach-shmobile/Makefile.boot
View File

@ -7,7 +7,6 @@ loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000

39
arch/arm/mach-shmobile/board-lager-reference.c
View File

@ -1,39 +0,0 @@
/*
* Lager board support - Reference DT implementation
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Simon Horman
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/init.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "common.h"
#include "r8a7790.h"
#include "rcar-gen2.h"
static const char *lager_boards_compat_dt[] __initdata = {
"renesas,lager",
"renesas,lager-reference",
NULL,
};
DT_MACHINE_START(LAGER_DT, "lager")
.smp = smp_ops(r8a7790_smp_ops),
.init_early = shmobile_init_delay,
.init_time = rcar_gen2_timer_init,
.init_late = shmobile_init_late,
.reserve = rcar_gen2_reserve,
.dt_compat = lager_boards_compat_dt,
MACHINE_END

827
arch/arm/mach-shmobile/board-lager.c
View File

@ -1,827 +0,0 @@
/*
* Lager board support
*
* Copyright (C) 2013-2014 Renesas Solutions Corp.
* Copyright (C) 2013 Magnus Damm
* Copyright (C) 2014 Cogent Embedded, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/leds.h>
#include <linux/mfd/tmio.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mmcif.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/mtd.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/camera-rcar.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/usb-rcar-gen2-phy.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/gpio-regulator.h>
#include <linux/regulator/machine.h>
#include <linux/sh_eth.h>
#include <linux/spi/flash.h>
#include <linux/spi/rspi.h>
#include <linux/spi/spi.h>
#include <linux/usb/phy.h>
#include <linux/usb/renesas_usbhs.h>
#include <media/soc_camera.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <sound/rcar_snd.h>
#include <sound/simple_card.h>
#include "common.h"
#include "irqs.h"
#include "r8a7790.h"
#include "rcar-gen2.h"
/*
* SSI-AK4643
*
* SW1: 1: AK4643
* 2: CN22
* 3: ADV7511
*
* this command is required when playback.
*
* # amixer set "LINEOUT Mixer DACL" on
*/
/*
* SDHI0 (CN8)
*
* JP3: pin1
* SW20: pin1
* GP5_24: 1: VDD 3.3V (defult)
* 0: VDD 0.0V
* GP5_29: 1: VccQ 3.3V (defult)
* 0: VccQ 1.8V
*
*/
/* LEDS */
static struct gpio_led lager_leds[] = {
{
.name = "led8",
.gpio = RCAR_GP_PIN(5, 17),
.default_state = LEDS_GPIO_DEFSTATE_ON,
}, {
.name = "led7",
.gpio = RCAR_GP_PIN(4, 23),
.default_state = LEDS_GPIO_DEFSTATE_ON,
}, {
.name = "led6",
.gpio = RCAR_GP_PIN(4, 22),
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
};
static const struct gpio_led_platform_data lager_leds_pdata __initconst = {
.leds = lager_leds,
.num_leds = ARRAY_SIZE(lager_leds),
};
/* GPIO KEY */
#define GPIO_KEY(c, g, d, ...) \
{ .code = c, .gpio = g, .desc = d, .active_low = 1, \
.wakeup = 1, .debounce_interval = 20 }
static struct gpio_keys_button gpio_buttons[] = {
GPIO_KEY(KEY_4, RCAR_GP_PIN(1, 28), "SW2-pin4"),
GPIO_KEY(KEY_3, RCAR_GP_PIN(1, 26), "SW2-pin3"),
GPIO_KEY(KEY_2, RCAR_GP_PIN(1, 24), "SW2-pin2"),
GPIO_KEY(KEY_1, RCAR_GP_PIN(1, 14), "SW2-pin1"),
};
static const struct gpio_keys_platform_data lager_keys_pdata __initconst = {
.buttons = gpio_buttons,
.nbuttons = ARRAY_SIZE(gpio_buttons),
};
/* Fixed 3.3V regulator to be used by MMCIF */
static struct regulator_consumer_supply fixed3v3_power_consumers[] =
{
REGULATOR_SUPPLY("vmmc", "sh_mmcif.1"),
};
/*
* SDHI regulator macro
*
** FIXME**
* Lager board vqmmc is provided via DA9063 PMIC chip,
* and we should use ${LINK}/drivers/mfd/da9063-* driver for it.
* but, it doesn't have regulator support at this point.
* It uses gpio-regulator for vqmmc as quick-hack.
*/
#define SDHI_REGULATOR(idx, vdd_pin, vccq_pin) \
static struct regulator_consumer_supply vcc_sdhi##idx##_consumer = \
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi." #idx); \
\
static struct regulator_init_data vcc_sdhi##idx##_init_data = { \
.constraints = { \
.valid_ops_mask = REGULATOR_CHANGE_STATUS, \
}, \
.consumer_supplies = &vcc_sdhi##idx##_consumer, \
.num_consumer_supplies = 1, \
}; \
\
static const struct fixed_voltage_config vcc_sdhi##idx##_info __initconst = {\
.supply_name = "SDHI" #idx "Vcc", \
.microvolts = 3300000, \
.gpio = vdd_pin, \
.enable_high = 1, \
.init_data = &vcc_sdhi##idx##_init_data, \
}; \
\
static struct regulator_consumer_supply vccq_sdhi##idx##_consumer = \
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi." #idx); \
\
static struct regulator_init_data vccq_sdhi##idx##_init_data = { \
.constraints = { \
.input_uV = 3300000, \
.min_uV = 1800000, \
.max_uV = 3300000, \
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | \
REGULATOR_CHANGE_STATUS, \
}, \
.consumer_supplies = &vccq_sdhi##idx##_consumer, \
.num_consumer_supplies = 1, \
}; \
\
static struct gpio vccq_sdhi##idx##_gpio = \
{ vccq_pin, GPIOF_OUT_INIT_HIGH, "vccq-sdhi" #idx }; \
\
static struct gpio_regulator_state vccq_sdhi##idx##_states[] = { \
{ .value = 1800000, .gpios = 0 }, \
{ .value = 3300000, .gpios = 1 }, \
}; \
\
static const struct gpio_regulator_config vccq_sdhi##idx##_info __initconst = {\
.supply_name = "vqmmc", \
.gpios = &vccq_sdhi##idx##_gpio, \
.nr_gpios = 1, \
.states = vccq_sdhi##idx##_states, \
.nr_states = ARRAY_SIZE(vccq_sdhi##idx##_states), \
.type = REGULATOR_VOLTAGE, \
.init_data = &vccq_sdhi##idx##_init_data, \
};
SDHI_REGULATOR(0, RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 29));
SDHI_REGULATOR(2, RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 30));
/* MMCIF */
static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = {
.caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
.clk_ctrl2_present = true,
.ccs_unsupported = true,
};
static const struct resource mmcif1_resources[] __initconst = {
DEFINE_RES_MEM(0xee220000, 0x80),
DEFINE_RES_IRQ(gic_spi(170)),
};
/* Ether */
static const struct sh_eth_plat_data ether_pdata __initconst = {
.phy = 0x1,
.phy_irq = irq_pin(0),
.edmac_endian = EDMAC_LITTLE_ENDIAN,
.phy_interface = PHY_INTERFACE_MODE_RMII,
.ether_link_active_low = 1,
};
static const struct resource ether_resources[] __initconst = {
DEFINE_RES_MEM(0xee700000, 0x400),
DEFINE_RES_IRQ(gic_spi(162)),
};
static const struct platform_device_info ether_info __initconst = {
.name = "r8a7790-ether",
.id = -1,
.res = ether_resources,
.num_res = ARRAY_SIZE(ether_resources),
.data = &ether_pdata,
.size_data = sizeof(ether_pdata),
.dma_mask = DMA_BIT_MASK(32),
};
/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64Mb) */
static struct mtd_partition spi_flash_part[] = {
/* Reserved for user loader program, read-only */
{
.name = "loader",
.offset = 0,
.size = SZ_256K,
.mask_flags = MTD_WRITEABLE,
},
/* Reserved for user program, read-only */
{
.name = "user",
.offset = MTDPART_OFS_APPEND,
.size = SZ_4M,
.mask_flags = MTD_WRITEABLE,
},
/* All else is writable (e.g. JFFS2) */
{
.name = "flash",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0,
},
};
static const struct flash_platform_data spi_flash_data = {
.name = "m25p80",
.parts = spi_flash_part,
.nr_parts = ARRAY_SIZE(spi_flash_part),
.type = "s25fl512s",
};
static const struct rspi_plat_data qspi_pdata __initconst = {
.num_chipselect = 1,
};
static const struct spi_board_info spi_info[] __initconst = {
{
.modalias = "m25p80",
.platform_data = &spi_flash_data,
.mode = SPI_MODE_0 | SPI_TX_QUAD | SPI_RX_QUAD,
.max_speed_hz = 30000000,
.bus_num = 0,
.chip_select = 0,
},
};
/* QSPI resource */
static const struct resource qspi_resources[] __initconst = {
DEFINE_RES_MEM(0xe6b10000, 0x1000),
DEFINE_RES_IRQ_NAMED(gic_spi(184), "mux"),
};
/* VIN */
static const struct resource vin_resources[] __initconst = {
/* VIN0 */
DEFINE_RES_MEM(0xe6ef0000, 0x1000),
DEFINE_RES_IRQ(gic_spi(188)),
/* VIN1 */
DEFINE_RES_MEM(0xe6ef1000, 0x1000),
DEFINE_RES_IRQ(gic_spi(189)),
};
static void __init lager_add_vin_device(unsigned idx,
struct rcar_vin_platform_data *pdata)
{
struct platform_device_info vin_info = {
.name = "r8a7790-vin",
.id = idx,
.res = &vin_resources[idx * 2],
.num_res = 2,
.dma_mask = DMA_BIT_MASK(32),
.data = pdata,
.size_data = sizeof(*pdata),
};
BUG_ON(idx > 1);
platform_device_register_full(&vin_info);
}
#define LAGER_CAMERA(idx, name, addr, pdata, flag) \
static struct i2c_board_info i2c_cam##idx##_device = { \
I2C_BOARD_INFO(name, addr), \
}; \
\
static struct rcar_vin_platform_data vin##idx##_pdata = { \
.flags = flag, \
}; \
\
static struct soc_camera_link cam##idx##_link = { \
.bus_id = idx, \
.board_info = &i2c_cam##idx##_device, \
.i2c_adapter_id = 2, \
.module_name = name, \
.priv = pdata, \
}
/* Camera 0 is not currently supported due to adv7612 support missing */
LAGER_CAMERA(1, "adv7180", 0x20, NULL, RCAR_VIN_BT656);
static void __init lager_add_camera1_device(void)
{
platform_device_register_data(NULL, "soc-camera-pdrv", 1,
&cam1_link, sizeof(cam1_link));
lager_add_vin_device(1, &vin1_pdata);
}
/* SATA1 */
static const struct resource sata1_resources[] __initconst = {
DEFINE_RES_MEM(0xee500000, 0x2000),
DEFINE_RES_IRQ(gic_spi(106)),
};
static const struct platform_device_info sata1_info __initconst = {
.name = "sata-r8a7790",
.id = 1,
.res = sata1_resources,
.num_res = ARRAY_SIZE(sata1_resources),
.dma_mask = DMA_BIT_MASK(32),
};
/* USBHS */
static const struct resource usbhs_resources[] __initconst = {
DEFINE_RES_MEM(0xe6590000, 0x100),
DEFINE_RES_IRQ(gic_spi(107)),
};
struct usbhs_private {
struct renesas_usbhs_platform_info info;
struct usb_phy *phy;
};
#define usbhs_get_priv(pdev) \
container_of(renesas_usbhs_get_info(pdev), struct usbhs_private, info)
static int usbhs_power_ctrl(struct platform_device *pdev,
void __iomem *base, int enable)
{
struct usbhs_private *priv = usbhs_get_priv(pdev);
if (!priv->phy)
return -ENODEV;
if (enable) {
int retval = usb_phy_init(priv->phy);
if (!retval)
retval = usb_phy_set_suspend(priv->phy, 0);
return retval;
}
usb_phy_set_suspend(priv->phy, 1);
usb_phy_shutdown(priv->phy);
return 0;
}
static int usbhs_hardware_init(struct platform_device *pdev)
{
struct usbhs_private *priv = usbhs_get_priv(pdev);
struct usb_phy *phy;
int ret;
/* USB0 Function - use PWEN as GPIO input to detect DIP Switch SW5
* setting to avoid VBUS short circuit due to wrong cable.
* PWEN should be pulled up high if USB Function is selected by SW5
*/
gpio_request_one(RCAR_GP_PIN(5, 18), GPIOF_IN, NULL); /* USB0_PWEN */
if (!gpio_get_value(RCAR_GP_PIN(5, 18))) {
pr_warn("Error: USB Function not selected - check SW5 + SW6\n");
ret = -ENOTSUPP;
goto error;
}
phy = usb_get_phy_dev(&pdev->dev, 0);
if (IS_ERR(phy)) {
ret = PTR_ERR(phy);
goto error;
}
priv->phy = phy;
return 0;
error:
gpio_free(RCAR_GP_PIN(5, 18));
return ret;
}
static int usbhs_hardware_exit(struct platform_device *pdev)
{
struct usbhs_private *priv = usbhs_get_priv(pdev);
if (!priv->phy)
return 0;
usb_put_phy(priv->phy);
priv->phy = NULL;
gpio_free(RCAR_GP_PIN(5, 18));
return 0;
}
static int usbhs_get_id(struct platform_device *pdev)
{
return USBHS_GADGET;
}
static u32 lager_usbhs_pipe_type[] = {
USB_ENDPOINT_XFER_CONTROL,
USB_ENDPOINT_XFER_ISOC,
USB_ENDPOINT_XFER_ISOC,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_INT,
USB_ENDPOINT_XFER_INT,
USB_ENDPOINT_XFER_INT,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
};
static struct usbhs_private usbhs_priv __initdata = {
.info = {
.platform_callback = {
.power_ctrl = usbhs_power_ctrl,
.hardware_init = usbhs_hardware_init,
.hardware_exit = usbhs_hardware_exit,
.get_id = usbhs_get_id,
},
.driver_param = {
.buswait_bwait = 4,
.pipe_type = lager_usbhs_pipe_type,
.pipe_size = ARRAY_SIZE(lager_usbhs_pipe_type),
},
}
};
static void __init lager_register_usbhs(void)
{
usb_bind_phy("renesas_usbhs", 0, "usb_phy_rcar_gen2");
platform_device_register_resndata(NULL,
"renesas_usbhs", -1,
usbhs_resources,
ARRAY_SIZE(usbhs_resources),
&usbhs_priv.info,
sizeof(usbhs_priv.info));
}
/* USBHS PHY */
static const struct rcar_gen2_phy_platform_data usbhs_phy_pdata __initconst = {
.chan0_pci = 0, /* Channel 0 is USBHS */
.chan2_pci = 1, /* Channel 2 is PCI USB */
};
static const struct resource usbhs_phy_resources[] __initconst = {
DEFINE_RES_MEM(0xe6590100, 0x100),
};
/* I2C */
static struct i2c_board_info i2c2_devices[] = {
{
I2C_BOARD_INFO("ak4643", 0x12),
}
};
/* Sound */
static struct resource rsnd_resources[] __initdata = {
[RSND_GEN2_SCU] = DEFINE_RES_MEM(0xec500000, 0x1000),
[RSND_GEN2_ADG] = DEFINE_RES_MEM(0xec5a0000, 0x100),
[RSND_GEN2_SSIU] = DEFINE_RES_MEM(0xec540000, 0x1000),
[RSND_GEN2_SSI] = DEFINE_RES_MEM(0xec541000, 0x1280),
};
static struct rsnd_ssi_platform_info rsnd_ssi[] = {
RSND_SSI(0, gic_spi(370), 0),
RSND_SSI(0, gic_spi(371), RSND_SSI_CLK_PIN_SHARE),
};
static struct rsnd_src_platform_info rsnd_src[2] = {
/* no member at this point */
};
static struct rsnd_dai_platform_info rsnd_dai = {
.playback = { .ssi = &rsnd_ssi[0], },
.capture = { .ssi = &rsnd_ssi[1], },
};
static struct rcar_snd_info rsnd_info = {
.flags = RSND_GEN2,
.ssi_info = rsnd_ssi,
.ssi_info_nr = ARRAY_SIZE(rsnd_ssi),
.src_info = rsnd_src,
.src_info_nr = ARRAY_SIZE(rsnd_src),
.dai_info = &rsnd_dai,
.dai_info_nr = 1,
};
static struct asoc_simple_card_info rsnd_card_info = {
.name = "AK4643",
.card = "SSI01-AK4643",
.codec = "ak4642-codec.2-0012",
.platform = "rcar_sound",
.daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
.cpu_dai = {
.name = "rcar_sound",
},
.codec_dai = {
.name = "ak4642-hifi",
.sysclk = 11289600,
},
};
static void __init lager_add_rsnd_device(void)
{
struct platform_device_info cardinfo = {
.name = "asoc-simple-card",
.id = -1,
.data = &rsnd_card_info,
.size_data = sizeof(struct asoc_simple_card_info),
.dma_mask = DMA_BIT_MASK(32),
};
i2c_register_board_info(2, i2c2_devices,
ARRAY_SIZE(i2c2_devices));
platform_device_register_resndata(
NULL, "rcar_sound", -1,
rsnd_resources, ARRAY_SIZE(rsnd_resources),
&rsnd_info, sizeof(rsnd_info));
platform_device_register_full(&cardinfo);
}
/* SDHI0 */
static struct sh_mobile_sdhi_info sdhi0_info __initdata = {
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
MMC_CAP_POWER_OFF_CARD,
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
TMIO_MMC_WRPROTECT_DISABLE,
};
static struct resource sdhi0_resources[] __initdata = {
DEFINE_RES_MEM(0xee100000, 0x200),
DEFINE_RES_IRQ(gic_spi(165)),
};
/* SDHI2 */
static struct sh_mobile_sdhi_info sdhi2_info __initdata = {
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
MMC_CAP_POWER_OFF_CARD,
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
TMIO_MMC_WRPROTECT_DISABLE,
};
static struct resource sdhi2_resources[] __initdata = {
DEFINE_RES_MEM(0xee140000, 0x100),
DEFINE_RES_IRQ(gic_spi(167)),
};
/* Internal PCI1 */
static const struct resource pci1_resources[] __initconst = {
DEFINE_RES_MEM(0xee0b0000, 0x10000), /* CFG */
DEFINE_RES_MEM(0xee0a0000, 0x10000), /* MEM */
DEFINE_RES_IRQ(gic_spi(112)),
};
static const struct platform_device_info pci1_info __initconst = {
.name = "pci-rcar-gen2",
.id = 1,
.res = pci1_resources,
.num_res = ARRAY_SIZE(pci1_resources),
.dma_mask = DMA_BIT_MASK(32),
};
static void __init lager_add_usb1_device(void)
{
platform_device_register_full(&pci1_info);
}
/* Internal PCI2 */
static const struct resource pci2_resources[] __initconst = {
DEFINE_RES_MEM(0xee0d0000, 0x10000), /* CFG */
DEFINE_RES_MEM(0xee0c0000, 0x10000), /* MEM */
DEFINE_RES_IRQ(gic_spi(113)),
};
static const struct platform_device_info pci2_info __initconst = {
.name = "pci-rcar-gen2",
.id = 2,
.res = pci2_resources,
.num_res = ARRAY_SIZE(pci2_resources),
.dma_mask = DMA_BIT_MASK(32),
};
static void __init lager_add_usb2_device(void)
{
platform_device_register_full(&pci2_info);
}
static const struct pinctrl_map lager_pinctrl_map[] = {
/* DU (CN10: ARGB0, CN13: LVDS) */
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
"du_rgb666", "du"),
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
"du_sync_1", "du"),
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
"du_clk_out_0", "du"),
/* I2C2 */
PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar.2", "pfc-r8a7790",
"i2c2", "i2c2"),
/* QSPI */
PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
"qspi_ctrl", "qspi"),
PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
"qspi_data4", "qspi"),
/* SCIF0 (CN19: DEBUG SERIAL0) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
"scif0_data", "scif0"),
/* SCIF1 (CN20: DEBUG SERIAL1) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
"scif1_data", "scif1"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790",
"sdhi0_cd", "sdhi0"),
/* SDHI2 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790",
"sdhi2_data4", "sdhi2"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790",
"sdhi2_ctrl", "sdhi2"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790",
"sdhi2_cd", "sdhi2"),
/* SSI (CN17: sound) */
PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
"ssi0129_ctrl", "ssi"),
PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
"ssi0_data", "ssi"),
PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
"ssi1_data", "ssi"),
PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
"audio_clk_a", "audio_clk"),
/* MMCIF1 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
"mmc1_data8", "mmc1"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
"mmc1_ctrl", "mmc1"),
/* Ether */
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
"eth_link", "eth"),
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
"eth_mdio", "eth"),
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
"eth_rmii", "eth"),
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
"intc_irq0", "intc"),
/* VIN0 */
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
"vin0_data24", "vin0"),
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
"vin0_sync", "vin0"),
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
"vin0_field", "vin0"),
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
"vin0_clkenb", "vin0"),
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
"vin0_clk", "vin0"),
/* VIN1 */
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
"vin1_data8", "vin1"),
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
"vin1_clk", "vin1"),
/* USB0 */
PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790",
"usb0_ovc_vbus", "usb0"),
/* USB1 */
PIN_MAP_MUX_GROUP_DEFAULT("pci-rcar-gen2.1", "pfc-r8a7790",
"usb1", "usb1"),
/* USB2 */
PIN_MAP_MUX_GROUP_DEFAULT("pci-rcar-gen2.2", "pfc-r8a7790",
"usb2", "usb2"),
};
static void __init lager_add_standard_devices(void)
{
int fixed_regulator_idx = 0;
int gpio_regulator_idx = 0;
r8a7790_clock_init();
pinctrl_register_mappings(lager_pinctrl_map,
ARRAY_SIZE(lager_pinctrl_map));
r8a7790_pinmux_init();
r8a7790_add_standard_devices();
platform_device_register_data(NULL, "leds-gpio", -1,
&lager_leds_pdata,
sizeof(lager_leds_pdata));
platform_device_register_data(NULL, "gpio-keys", -1,
&lager_keys_pdata,
sizeof(lager_keys_pdata));
regulator_register_always_on(fixed_regulator_idx++,
"fixed-3.3V", fixed3v3_power_consumers,
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
platform_device_register_resndata(NULL, "sh_mmcif", 1,
mmcif1_resources, ARRAY_SIZE(mmcif1_resources),
&mmcif1_pdata, sizeof(mmcif1_pdata));
platform_device_register_full(&ether_info);
platform_device_register_resndata(NULL, "qspi", 0,
qspi_resources,
ARRAY_SIZE(qspi_resources),
&qspi_pdata, sizeof(qspi_pdata));
spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
platform_device_register_data(NULL, "reg-fixed-voltage", fixed_regulator_idx++,
&vcc_sdhi0_info, sizeof(struct fixed_voltage_config));
platform_device_register_data(NULL, "reg-fixed-voltage", fixed_regulator_idx++,
&vcc_sdhi2_info, sizeof(struct fixed_voltage_config));
platform_device_register_data(NULL, "gpio-regulator", gpio_regulator_idx++,
&vccq_sdhi0_info, sizeof(struct gpio_regulator_config));
platform_device_register_data(NULL, "gpio-regulator", gpio_regulator_idx++,
&vccq_sdhi2_info, sizeof(struct gpio_regulator_config));
lager_add_camera1_device();
platform_device_register_full(&sata1_info);
platform_device_register_resndata(NULL, "usb_phy_rcar_gen2",
-1, usbhs_phy_resources,
ARRAY_SIZE(usbhs_phy_resources),
&usbhs_phy_pdata,
sizeof(usbhs_phy_pdata));
lager_register_usbhs();
lager_add_usb1_device();
lager_add_usb2_device();
lager_add_rsnd_device();
platform_device_register_resndata(NULL, "sh_mobile_sdhi", 0,
sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
&sdhi0_info, sizeof(struct sh_mobile_sdhi_info));
platform_device_register_resndata(NULL, "sh_mobile_sdhi", 2,
sdhi2_resources, ARRAY_SIZE(sdhi2_resources),
&sdhi2_info, sizeof(struct sh_mobile_sdhi_info));
}
/*
* Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds
* to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
* 14-15. We have to set them back to 01 from the default 00 value each time
* the PHY is reset. It's also important because the PHY's LED0 signal is
* connected to SoC's ETH_LINK signal and in the PHY's default mode it will
* bounce on and off after each packet, which we apparently want to avoid.
*/
static int lager_ksz8041_fixup(struct phy_device *phydev)
{
u16 phyctrl1 = phy_read(phydev, 0x1e);
phyctrl1 &= ~0xc000;
phyctrl1 |= 0x4000;
return phy_write(phydev, 0x1e, phyctrl1);
}
static void __init lager_init(void)
{
lager_add_standard_devices();
irq_set_irq_type(irq_pin(0), IRQ_TYPE_LEVEL_LOW);
if (IS_ENABLED(CONFIG_PHYLIB))
phy_register_fixup_for_id("r8a7790-ether-ff:01",
lager_ksz8041_fixup);
}
static const char * const lager_boards_compat_dt[] __initconst = {
"renesas,lager",
NULL,
};
DT_MACHINE_START(LAGER_DT, "lager")
.smp = smp_ops(r8a7790_smp_ops),
.init_early = shmobile_init_delay,
.init_time = rcar_gen2_timer_init,
.init_machine = lager_init,
.init_late = shmobile_init_late,
.reserve = rcar_gen2_reserve,
.dt_compat = lager_boards_compat_dt,
MACHINE_END

459
arch/arm/mach-shmobile/clock-r8a7790.c
View File

@ -1,459 +0,0 @@
/*
* r8a7790 clock framework support
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include "clock.h"
#include "common.h"
#include "r8a7790.h"
#include "rcar-gen2.h"
/*
* MD EXTAL PLL0 PLL1 PLL3
* 14 13 19 (MHz) *1 *1
*---------------------------------------------------
* 0 0 0 15 x 1 x172/2 x208/2 x106
* 0 0 1 15 x 1 x172/2 x208/2 x88
* 0 1 0 20 x 1 x130/2 x156/2 x80
* 0 1 1 20 x 1 x130/2 x156/2 x66
* 1 0 0 26 / 2 x200/2 x240/2 x122
* 1 0 1 26 / 2 x200/2 x240/2 x102
* 1 1 0 30 / 2 x172/2 x208/2 x106
* 1 1 1 30 / 2 x172/2 x208/2 x88
*
* *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
* see "p1 / 2" on R8A7790_CLOCK_ROOT() below
*/
#define CPG_BASE 0xe6150000
#define CPG_LEN 0x1000
#define SMSTPCR1 0xe6150134
#define SMSTPCR2 0xe6150138
#define SMSTPCR3 0xe615013c
#define SMSTPCR5 0xe6150144
#define SMSTPCR7 0xe615014c
#define SMSTPCR8 0xe6150990
#define SMSTPCR9 0xe6150994
#define SMSTPCR10 0xe6150998
#define MSTPSR1 IOMEM(0xe6150038)
#define MSTPSR2 IOMEM(0xe6150040)
#define MSTPSR3 IOMEM(0xe6150048)
#define MSTPSR5 IOMEM(0xe615003c)
#define MSTPSR7 IOMEM(0xe61501c4)
#define MSTPSR8 IOMEM(0xe61509a0)
#define MSTPSR9 IOMEM(0xe61509a4)
#define MSTPSR10 IOMEM(0xe61509a8)
#define SDCKCR 0xE6150074
#define SD2CKCR 0xE6150078
#define SD3CKCR 0xE615026C
#define MMC0CKCR 0xE6150240
#define MMC1CKCR 0xE6150244
#define SSPCKCR 0xE6150248
#define SSPRSCKCR 0xE615024C
static struct clk_mapping cpg_mapping = {
.phys = CPG_BASE,
.len = CPG_LEN,
};
static struct clk extal_clk = {
/* .rate will be updated on r8a7790_clock_init() */
.mapping = &cpg_mapping,
};
static struct sh_clk_ops followparent_clk_ops = {
.recalc = followparent_recalc,
};
static struct clk main_clk = {
/* .parent will be set r8a7790_clock_init */
.ops = &followparent_clk_ops,
};
static struct clk audio_clk_a = {
};
static struct clk audio_clk_b = {
};
static struct clk audio_clk_c = {
};
/*
* clock ratio of these clock will be updated
* on r8a7790_clock_init()
*/
SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
/* fixed ratio clock */
SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2);
SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12);
SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48);
SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8);
SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4);
SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024));
SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4);
SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8);
SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8);
SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
static struct clk *main_clks[] = {
&audio_clk_a,
&audio_clk_b,
&audio_clk_c,
&extal_clk,
&extal_div2_clk,
&main_clk,
&pll1_clk,
&pll1_div2_clk,
&pll3_clk,
&lb_clk,
&qspi_clk,
&zg_clk,
&zx_clk,
&zs_clk,
&hp_clk,
&i_clk,
&b_clk,
&p_clk,
&cl_clk,
&m2_clk,
&imp_clk,
&rclk_clk,
&oscclk_clk,
&zb3_clk,
&zb3d2_clk,
&ddr_clk,
&mp_clk,
&cp_clk,
};
/* SDHI (DIV4) clock */
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = divisors,
.nr_divisors = ARRAY_SIZE(divisors),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
};
enum {
DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
};
static struct clk div4_clks[DIV4_NR] = {
[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
};
/* DIV6 clocks */
enum {
DIV6_SD2, DIV6_SD3,
DIV6_MMC0, DIV6_MMC1,
DIV6_SSP, DIV6_SSPRS,
DIV6_NR
};
static struct clk div6_clks[DIV6_NR] = {
[DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
[DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
[DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
[DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
[DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
[DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
};
/* MSTP */
enum {
MSTP1017, /* parent of SCU */
MSTP1031, MSTP1030,
MSTP1029, MSTP1028, MSTP1027, MSTP1026, MSTP1025, MSTP1024, MSTP1023, MSTP1022,
MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
MSTP931, MSTP930, MSTP929, MSTP928,
MSTP917,
MSTP815, MSTP814,
MSTP813,
MSTP811, MSTP810, MSTP809, MSTP808,
MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
MSTP717, MSTP716,
MSTP704, MSTP703,
MSTP522,
MSTP502, MSTP501,
MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
MSTP124,
MSTP_NR
};
static struct clk mstp_clks[MSTP_NR] = {
[MSTP1031] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 31, MSTPSR10, 0), /* SCU0 */
[MSTP1030] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 30, MSTPSR10, 0), /* SCU1 */
[MSTP1029] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 29, MSTPSR10, 0), /* SCU2 */
[MSTP1028] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 28, MSTPSR10, 0), /* SCU3 */
[MSTP1027] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 27, MSTPSR10, 0), /* SCU4 */
[MSTP1026] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 26, MSTPSR10, 0), /* SCU5 */
[MSTP1025] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 25, MSTPSR10, 0), /* SCU6 */
[MSTP1024] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 24, MSTPSR10, 0), /* SCU7 */
[MSTP1023] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 23, MSTPSR10, 0), /* SCU8 */
[MSTP1022] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 22, MSTPSR10, 0), /* SCU9 */
[MSTP1017] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 17, MSTPSR10, 0), /* SCU */
[MSTP1015] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 15, MSTPSR10, 0), /* SSI0 */
[MSTP1014] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 14, MSTPSR10, 0), /* SSI1 */
[MSTP1013] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 13, MSTPSR10, 0), /* SSI2 */
[MSTP1012] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 12, MSTPSR10, 0), /* SSI3 */
[MSTP1011] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 11, MSTPSR10, 0), /* SSI4 */
[MSTP1010] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 10, MSTPSR10, 0), /* SSI5 */
[MSTP1009] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 9, MSTPSR10, 0), /* SSI6 */
[MSTP1008] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 8, MSTPSR10, 0), /* SSI7 */
[MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
[MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
[MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
[MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
[MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
[MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
[MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
[MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
[MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
[MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
[MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 8, MSTPSR8, 0), /* VIN3 */
[MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
[MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
[MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
[MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
[MSTP722] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 22, MSTPSR7, 0), /* DU2 */
[MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
[MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
[MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */
[MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
[MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
[MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
[MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
[MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
[MSTP315] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, MSTPSR3, 0), /* MMC0 */
[MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
[MSTP313] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD1], SMSTPCR3, 13, MSTPSR3, 0), /* SDHI1 */
[MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI2 */
[MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD3], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI3 */
[MSTP305] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, MSTPSR3, 0), /* MMC1 */
[MSTP304] = SH_CLK_MSTP32_STS(&cp_clk, SMSTPCR3, 4, MSTPSR3, 0), /* TPU0 */
[MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
[MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
[MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
[MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
[MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
[MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
[MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
};
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
CLKDEV_CON_ID("main", &main_clk),
CLKDEV_CON_ID("pll1", &pll1_clk),
CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
CLKDEV_CON_ID("pll3", &pll3_clk),
CLKDEV_CON_ID("zg", &zg_clk),
CLKDEV_CON_ID("zx", &zx_clk),
CLKDEV_CON_ID("zs", &zs_clk),
CLKDEV_CON_ID("hp", &hp_clk),
CLKDEV_CON_ID("i", &i_clk),
CLKDEV_CON_ID("b", &b_clk),
CLKDEV_CON_ID("lb", &lb_clk),
CLKDEV_CON_ID("p", &p_clk),
CLKDEV_CON_ID("cl", &cl_clk),
CLKDEV_CON_ID("m2", &m2_clk),
CLKDEV_CON_ID("imp", &imp_clk),
CLKDEV_CON_ID("rclk", &rclk_clk),
CLKDEV_CON_ID("oscclk", &oscclk_clk),
CLKDEV_CON_ID("zb3", &zb3_clk),
CLKDEV_CON_ID("zb3d2", &zb3d2_clk),
CLKDEV_CON_ID("ddr", &ddr_clk),
CLKDEV_CON_ID("mp", &mp_clk),
CLKDEV_CON_ID("qspi", &qspi_clk),
CLKDEV_CON_ID("cp", &cp_clk),
/* DIV4 */
CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]),
/* DIV6 */
CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]),
CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
/* MSTP */
CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
/* ICK */
CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]),
CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP1031]),
CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP1030]),
CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP1029]),
CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP1028]),
CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP1027]),
CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP1026]),
CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP1025]),
CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP1024]),
CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP1023]),
CLKDEV_ICK_ID("src.9", "rcar_sound", &mstp_clks[MSTP1022]),
CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
};
#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
extal_clk.rate = e * 1000 * 1000; \
main_clk.parent = m; \
SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
if (mode & MD(19)) \
SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
else \
SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
void __init r8a7790_clock_init(void)
{
u32 mode = rcar_gen2_read_mode_pins();
int k, ret = 0;
switch (mode & (MD(14) | MD(13))) {
case 0:
R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
break;
case MD(13):
R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
break;
case MD(14):
R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
break;
case MD(13) | MD(14):
R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
break;
}
if (mode & (MD(18)))
SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
else
SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
else
SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
shmobile_clk_init();
else
panic("failed to setup r8a7790 clocks\n");
}

28
arch/arm/mach-shmobile/r8a7790.h
View File

@ -1,34 +1,6 @@
#ifndef __ASM_R8A7790_H__
#define __ASM_R8A7790_H__
/* DMA slave IDs */
enum {
RCAR_DMA_SLAVE_INVALID,
AUDIO_DMAC_SLAVE_SSI0_TX,
AUDIO_DMAC_SLAVE_SSI0_RX,
AUDIO_DMAC_SLAVE_SSI1_TX,
AUDIO_DMAC_SLAVE_SSI1_RX,
AUDIO_DMAC_SLAVE_SSI2_TX,
AUDIO_DMAC_SLAVE_SSI2_RX,
AUDIO_DMAC_SLAVE_SSI3_TX,
AUDIO_DMAC_SLAVE_SSI3_RX,
AUDIO_DMAC_SLAVE_SSI4_TX,
AUDIO_DMAC_SLAVE_SSI4_RX,
AUDIO_DMAC_SLAVE_SSI5_TX,
AUDIO_DMAC_SLAVE_SSI5_RX,
AUDIO_DMAC_SLAVE_SSI6_TX,
AUDIO_DMAC_SLAVE_SSI6_RX,
AUDIO_DMAC_SLAVE_SSI7_TX,
AUDIO_DMAC_SLAVE_SSI7_RX,
AUDIO_DMAC_SLAVE_SSI8_TX,
AUDIO_DMAC_SLAVE_SSI8_RX,
AUDIO_DMAC_SLAVE_SSI9_TX,
AUDIO_DMAC_SLAVE_SSI9_RX,
};
void r8a7790_add_standard_devices(void);
void r8a7790_clock_init(void);
void r8a7790_pinmux_init(void);
void r8a7790_pm_init(void);
extern struct smp_operations r8a7790_smp_ops;

284
arch/arm/mach-shmobile/setup-r8a7790.c
View File

@ -14,295 +14,14 @@
* GNU General Public License for more details.
*/
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/serial_sci.h>
#include <linux/sh_dma.h>
#include <linux/sh_timer.h>
#include <linux/init.h>
#include <asm/mach/arch.h>
#include "common.h"
#include "dma-register.h"
#include "irqs.h"
#include "r8a7790.h"
#include "rcar-gen2.h"
/* Audio-DMAC */
#define AUDIO_DMAC_SLAVE(_id, _addr, t, r) \
{ \
.slave_id = AUDIO_DMAC_SLAVE_## _id ##_TX, \
.addr = _addr + 0x8, \
.chcr = CHCR_TX(XMIT_SZ_32BIT), \
.mid_rid = t, \
}, { \
.slave_id = AUDIO_DMAC_SLAVE_## _id ##_RX, \
.addr = _addr + 0xc, \
.chcr = CHCR_RX(XMIT_SZ_32BIT), \
.mid_rid = r, \
}
static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
};
#define DMAE_CHANNEL(a, b) \
{ \
.offset = (a) - 0x20, \
.dmars = (a) - 0x20 + 0x40, \
.chclr_bit = (b), \
.chclr_offset = 0x80 - 0x20, \
}
static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
DMAE_CHANNEL(0x8000, 0),
DMAE_CHANNEL(0x8080, 1),
DMAE_CHANNEL(0x8100, 2),
DMAE_CHANNEL(0x8180, 3),
DMAE_CHANNEL(0x8200, 4),
DMAE_CHANNEL(0x8280, 5),
DMAE_CHANNEL(0x8300, 6),
DMAE_CHANNEL(0x8380, 7),
DMAE_CHANNEL(0x8400, 8),
DMAE_CHANNEL(0x8480, 9),
DMAE_CHANNEL(0x8500, 10),
DMAE_CHANNEL(0x8580, 11),
DMAE_CHANNEL(0x8600, 12),
};
static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
.slave = r8a7790_audio_dmac_slaves,
.slave_num = ARRAY_SIZE(r8a7790_audio_dmac_slaves),
.channel = r8a7790_audio_dmac_channels,
.channel_num = ARRAY_SIZE(r8a7790_audio_dmac_channels),
.ts_low_shift = TS_LOW_SHIFT,
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
.ts_high_shift = TS_HI_SHIFT,
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
.ts_shift = dma_ts_shift,
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
.dmaor_init = DMAOR_DME,
.chclr_present = 1,
.chclr_bitwise = 1,
};
static struct resource r8a7790_audio_dmac_resources[] = {
/* Channel registers and DMAOR for low */
DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
DEFINE_RES_IRQ(gic_spi(346)),
DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),
/* Channel registers and DMAOR for hi */
DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
DEFINE_RES_IRQ(gic_spi(347)),
DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
};
#define r8a7790_register_audio_dmac(id) \
platform_device_register_resndata( \
NULL, "sh-dma-engine", id, \
&r8a7790_audio_dmac_resources[id * 3], 3, \
&r8a7790_audio_dmac_platform_data, \
sizeof(r8a7790_audio_dmac_platform_data))
static const struct resource pfc_resources[] __initconst = {
DEFINE_RES_MEM(0xe6060000, 0x250),
};
#define r8a7790_register_pfc() \
platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \
ARRAY_SIZE(pfc_resources))
#define R8A7790_GPIO(idx) \
static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
}; \
\
static const struct gpio_rcar_config \
r8a7790_gpio##idx##_platform_data __initconst = { \
.gpio_base = 32 * (idx), \
.irq_base = 0, \
.number_of_pins = 32, \
.pctl_name = "pfc-r8a7790", \
.has_both_edge_trigger = 1, \
}; \
R8A7790_GPIO(0);
R8A7790_GPIO(1);
R8A7790_GPIO(2);
R8A7790_GPIO(3);
R8A7790_GPIO(4);
R8A7790_GPIO(5);
#define r8a7790_register_gpio(idx) \
platform_device_register_resndata(NULL, "gpio_rcar", idx, \
r8a7790_gpio##idx##_resources, \
ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
&r8a7790_gpio##idx##_platform_data, \
sizeof(r8a7790_gpio##idx##_platform_data))
static struct resource i2c_resources[] __initdata = {
/* I2C0 */
DEFINE_RES_MEM(0xE6508000, 0x40),
DEFINE_RES_IRQ(gic_spi(287)),
/* I2C1 */
DEFINE_RES_MEM(0xE6518000, 0x40),
DEFINE_RES_IRQ(gic_spi(288)),
/* I2C2 */
DEFINE_RES_MEM(0xE6530000, 0x40),
DEFINE_RES_IRQ(gic_spi(286)),
/* I2C3 */
DEFINE_RES_MEM(0xE6540000, 0x40),
DEFINE_RES_IRQ(gic_spi(290)),
};
#define r8a7790_register_i2c(idx) \
platform_device_register_simple( \
"i2c-rcar_gen2", idx, \
i2c_resources + (2 * idx), 2); \
void __init r8a7790_pinmux_init(void)
{
r8a7790_register_pfc();
r8a7790_register_gpio(0);
r8a7790_register_gpio(1);
r8a7790_register_gpio(2);
r8a7790_register_gpio(3);
r8a7790_register_gpio(4);
r8a7790_register_gpio(5);
}
#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.scscr = _scscr, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}
#define R8A7790_SCIF(index, baseaddr, irq) \
__R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \
index, baseaddr, irq)
#define R8A7790_SCIFA(index, baseaddr, irq) \
__R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
index, baseaddr, irq)
#define R8A7790_SCIFB(index, baseaddr, irq) \
__R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
index, baseaddr, irq)
#define R8A7790_HSCIF(index, baseaddr, irq) \
__R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \
index, baseaddr, irq)
R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
#define r8a7790_register_scif(index) \
platform_device_register_resndata(NULL, "sh-sci", index, \
scif##index##_resources, \
ARRAY_SIZE(scif##index##_resources), \
&scif##index##_platform_data, \
sizeof(scif##index##_platform_data))
static const struct renesas_irqc_config irqc0_data __initconst = {
.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
};
static const struct resource irqc0_resources[] __initconst = {
DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
};
#define r8a7790_register_irqc(idx) \
platform_device_register_resndata(NULL, "renesas_irqc", \
idx, irqc##idx##_resources, \
ARRAY_SIZE(irqc##idx##_resources), \
&irqc##idx##_data, \
sizeof(struct renesas_irqc_config))
static const struct resource thermal_resources[] __initconst = {
DEFINE_RES_MEM(0xe61f0000, 0x14),
DEFINE_RES_MEM(0xe61f0100, 0x38),
DEFINE_RES_IRQ(gic_spi(69)),
};
#define r8a7790_register_thermal() \
platform_device_register_simple("rcar_thermal", -1, \
thermal_resources, \
ARRAY_SIZE(thermal_resources))
static struct sh_timer_config cmt0_platform_data = {
.channels_mask = 0x60,
};
static struct resource cmt0_resources[] = {
DEFINE_RES_MEM(0xffca0000, 0x1004),
DEFINE_RES_IRQ(gic_spi(142)),
};
#define r8a7790_register_cmt(idx) \
platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \
idx, cmt##idx##_resources, \
ARRAY_SIZE(cmt##idx##_resources), \
&cmt##idx##_platform_data, \
sizeof(struct sh_timer_config))
void __init r8a7790_add_standard_devices(void)
{
r8a7790_register_scif(0);
r8a7790_register_scif(1);
r8a7790_register_scif(2);
r8a7790_register_scif(3);
r8a7790_register_scif(4);
r8a7790_register_scif(5);
r8a7790_register_scif(6);
r8a7790_register_scif(7);
r8a7790_register_scif(8);
r8a7790_register_scif(9);
r8a7790_register_cmt(0);
r8a7790_register_irqc(0);
r8a7790_register_thermal();
r8a7790_register_i2c(0);
r8a7790_register_i2c(1);
r8a7790_register_i2c(2);
r8a7790_register_i2c(3);
r8a7790_register_audio_dmac(0);
r8a7790_register_audio_dmac(1);
}
#ifdef CONFIG_USE_OF
static const char * const r8a7790_boards_compat_dt[] __initconst = {
"renesas,r8a7790",
NULL,
@ -316,4 +35,3 @@ DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
.reserve = rcar_gen2_reserve,
.dt_compat = r8a7790_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */