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drm/i915/psr: Print PSR_STATUS when PSR idle wait times out. 

Knowing the status of the PSR HW state machine is useful for debug,
especially since we are seeing errors with PSR2 in CI.

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180821221156.2442-1-dhinakaran.pandiyan@intel.com
hifive-unleashed-5.1
Dhinakaran Pandiyan 2018-08-21 15:11:54 -07:00
parent df4f94e810
commit 63ec132d5b
3 changed files with 12 additions and 6 deletions
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3
drivers/gpu/drm/i915/intel_drv.h
View File

@ -1947,7 +1947,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
void intel_psr_short_pulse(struct intel_dp *intel_dp);
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
u32 *out_value);
/* intel_runtime_pm.c */
int intel_power_domains_init(struct drm_i915_private *);

9
drivers/gpu/drm/i915/intel_psr.c
View File

@ -766,7 +766,8 @@ void intel_psr_disable(struct intel_dp *intel_dp,
cancel_work_sync(&dev_priv->psr.work);
}
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
u32 *out_value)
{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@ -799,8 +800,10 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
* 6 ms of exit training time + 1.5 ms of aux channel
* handshake. 50 msec is defesive enough to cover everything.
*/
return intel_wait_for_register(dev_priv, reg, mask,
EDP_PSR_STATUS_STATE_IDLE, 50);
return __intel_wait_for_register(dev_priv, reg, mask,
EDP_PSR_STATUS_STATE_IDLE, 2, 50,
out_value);
}
static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)

6
drivers/gpu/drm/i915/intel_sprite.c
View File

@ -83,6 +83,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
DEFINE_WAIT(wait);
u32 psr_status;
vblank_start = adjusted_mode->crtc_vblank_start;
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
@ -104,8 +105,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
* VBL interrupts will start the PSR exit and prevent a PSR
* re-entry as well.
*/
if (intel_psr_wait_for_idle(new_crtc_state))
DRM_ERROR("PSR idle timed out, atomic update may fail\n");
if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n",
psr_status);
local_irq_disable();