staging: comedi: addi_apci_1564: store PCI BAR 1 base address in private data
According to ADDI-DATA, only the PLD Revision 2.x versions of the APCI-1564 have the 3 counters. The base address for these counters is found in PCI BAR 1. For aesthetics, save this base address in the private data. The dev->iobase can then be used for the main registers of the board. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -47,7 +47,7 @@
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#define APCI1564_TIMER_WARN_TIMEBASE_REG 0x64
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/*
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* dev->iobase Register Map
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* devpriv->counters Register Map
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*/
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#define APCI1564_COUNTER_REG(x) (0x00 + ((x) * 0x20))
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#define APCI1564_COUNTER_RELOAD_REG(x) (0x04 + ((x) * 0x20))
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@ -93,12 +93,12 @@ static int apci1564_timer_config(struct comedi_device *dev,
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outl(0x0, devpriv->amcc_iobase + APCI1564_DI_IRQ_REG);
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outl(0x0, devpriv->amcc_iobase + APCI1564_DO_IRQ_REG);
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outl(0x0, devpriv->amcc_iobase + APCI1564_WDOG_IRQ_REG);
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outl(0x0, dev->iobase +
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APCI1564_COUNTER_IRQ_REG(0));
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outl(0x0, dev->iobase +
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APCI1564_COUNTER_IRQ_REG(1));
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outl(0x0, dev->iobase +
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APCI1564_COUNTER_IRQ_REG(2));
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outl(0x0,
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devpriv->counters + APCI1564_COUNTER_IRQ_REG(0));
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outl(0x0,
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devpriv->counters + APCI1564_COUNTER_IRQ_REG(1));
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outl(0x0,
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devpriv->counters + APCI1564_COUNTER_IRQ_REG(2));
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} else {
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/* disable Timer interrupt */
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outl(0x0, devpriv->amcc_iobase + APCI1564_TIMER_CTRL_REG);
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@ -118,16 +118,16 @@ static int apci1564_timer_config(struct comedi_device *dev,
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devpriv->timer_select_mode = ADDIDATA_COUNTER;
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/* First Stop The Counter */
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ul_Command1 = inl(dev->iobase +
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APCI1564_COUNTER_CTRL_REG(chan));
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ul_Command1 = inl(devpriv->counters +
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APCI1564_COUNTER_CTRL_REG(chan));
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ul_Command1 = ul_Command1 & 0xFFFFF9FEUL;
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/* Stop The Timer */
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outl(ul_Command1, dev->iobase +
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APCI1564_COUNTER_CTRL_REG(chan));
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outl(ul_Command1,
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devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
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/* Set the reload value */
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outl(data[3], dev->iobase +
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APCI1564_COUNTER_RELOAD_REG(chan));
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outl(data[3],
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devpriv->counters + APCI1564_COUNTER_RELOAD_REG(chan));
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/* Set the mode : */
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/* - Disable the hardware */
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@ -140,18 +140,18 @@ static int apci1564_timer_config(struct comedi_device *dev,
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ul_Command1 =
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(ul_Command1 & 0xFFFC19E2UL) | 0x80000UL |
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(unsigned int) ((unsigned int) data[4] << 16UL);
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outl(ul_Command1, dev->iobase +
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APCI1564_COUNTER_CTRL_REG(chan));
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outl(ul_Command1,
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devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
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/* Enable or Disable Interrupt */
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ul_Command1 = (ul_Command1 & 0xFFFFF9FD) | (data[1] << 1);
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outl(ul_Command1, dev->iobase +
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APCI1564_COUNTER_CTRL_REG(chan));
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outl(ul_Command1,
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devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
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/* Set the Up/Down selection */
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ul_Command1 = (ul_Command1 & 0xFFFBF9FFUL) | (data[6] << 18);
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outl(ul_Command1, dev->iobase +
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APCI1564_COUNTER_CTRL_REG(chan));
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outl(ul_Command1,
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devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
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} else {
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dev_err(dev->class_dev, "Invalid subdevice.\n");
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}
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@ -188,9 +188,8 @@ static int apci1564_timer_write(struct comedi_device *dev,
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outl(ul_Command1, devpriv->amcc_iobase + APCI1564_TIMER_CTRL_REG);
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}
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} else if (devpriv->timer_select_mode == ADDIDATA_COUNTER) {
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ul_Command1 =
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inl(dev->iobase +
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APCI1564_COUNTER_CTRL_REG(chan));
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ul_Command1 = inl(devpriv->counters +
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APCI1564_COUNTER_CTRL_REG(chan));
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if (data[1] == 1) {
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/* Start the Counter subdevice */
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ul_Command1 = (ul_Command1 & 0xFFFFF9FFUL) | 0x1UL;
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@ -202,8 +201,8 @@ static int apci1564_timer_write(struct comedi_device *dev,
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/* Clears the Counter subdevice */
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ul_Command1 = (ul_Command1 & 0xFFFFF9FFUL) | 0x400;
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}
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outl(ul_Command1, dev->iobase +
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APCI1564_COUNTER_CTRL_REG(chan));
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outl(ul_Command1,
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devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
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} else {
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dev_err(dev->class_dev, "Invalid subdevice.\n");
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}
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@ -230,12 +229,10 @@ static int apci1564_timer_read(struct comedi_device *dev,
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data[1] = inl(devpriv->amcc_iobase + APCI1564_TIMER_REG);
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} else if (devpriv->timer_select_mode == ADDIDATA_COUNTER) {
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/* Read the Counter Actual Value. */
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data[0] =
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inl(dev->iobase +
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APCI1564_COUNTER_REG(chan));
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ul_Command1 =
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inl(dev->iobase +
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APCI1564_COUNTER_STATUS_REG(chan));
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data[0] = inl(devpriv->counters +
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APCI1564_COUNTER_REG(chan));
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ul_Command1 = inl(devpriv->counters +
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APCI1564_COUNTER_STATUS_REG(chan));
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/* Get the software trigger status */
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data[1] = (unsigned char) ((ul_Command1 >> 1) & 1);
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@ -31,6 +31,7 @@
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#include "addi_watchdog.h"
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struct apci1564_private {
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unsigned long counters; /* base address of 32-bit counters */
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unsigned int amcc_iobase; /* base of AMCC I/O registers */
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unsigned int mode1; /* riding-edge/high level channels */
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unsigned int mode2; /* falling-edge/low level channels */
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@ -63,9 +64,9 @@ static int apci1564_reset(struct comedi_device *dev)
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outl(0x0, devpriv->amcc_iobase + APCI1564_TIMER_RELOAD_REG);
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/* Reset the counter registers */
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outl(0x0, dev->iobase + APCI1564_COUNTER_CTRL_REG(0));
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outl(0x0, dev->iobase + APCI1564_COUNTER_CTRL_REG(1));
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outl(0x0, dev->iobase + APCI1564_COUNTER_CTRL_REG(2));
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outl(0x0, devpriv->counters + APCI1564_COUNTER_CTRL_REG(0));
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outl(0x0, devpriv->counters + APCI1564_COUNTER_CTRL_REG(1));
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outl(0x0, devpriv->counters + APCI1564_COUNTER_CTRL_REG(2));
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return 0;
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}
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@ -108,20 +109,21 @@ static irqreturn_t apci1564_interrupt(int irq, void *d)
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}
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for (chan = 0; chan < 4; chan++) {
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status = inl(dev->iobase + APCI1564_COUNTER_IRQ_REG(chan));
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status = inl(devpriv->counters +
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APCI1564_COUNTER_IRQ_REG(chan));
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if (status & 0x01) {
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/* Disable Counter Interrupt */
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ctrl = inl(dev->iobase +
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APCI1564_COUNTER_CTRL_REG(chan));
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outl(0x0, dev->iobase +
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APCI1564_COUNTER_CTRL_REG(chan));
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ctrl = inl(devpriv->counters +
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APCI1564_COUNTER_CTRL_REG(chan));
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outl(0x0, devpriv->counters +
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APCI1564_COUNTER_CTRL_REG(chan));
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/* Send a signal to from kernel to user space */
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send_sig(SIGIO, devpriv->tsk_current, 0);
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/* Enable Counter Interrupt */
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outl(ctrl, dev->iobase +
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APCI1564_COUNTER_CTRL_REG(chan));
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outl(ctrl, devpriv->counters +
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APCI1564_COUNTER_CTRL_REG(chan));
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}
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}
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@ -369,8 +371,9 @@ static int apci1564_auto_attach(struct comedi_device *dev,
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if (ret)
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return ret;
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dev->iobase = pci_resource_start(pcidev, 1);
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/* PLD Revision 2.x I/O Mapping */
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devpriv->amcc_iobase = pci_resource_start(pcidev, 0);
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devpriv->counters = pci_resource_start(pcidev, 1);
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apci1564_reset(dev);
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