ARM: KVM: fix vgic V7 assembler code to work in BE image
The vgic h/w registers are little endian; when BE asm code reads/writes from/to them, it needs to do byteswap after/before. Byteswap code uses ARM_BE8 wrapper to add swap only if CONFIG_CPU_BIG_ENDIAN is configured. Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -1,4 +1,5 @@
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#include <linux/irqchip/arm-gic.h>
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#include <asm/assembler.h>
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#define VCPU_USR_REG(_reg_nr) (VCPU_USR_REGS + (_reg_nr * 4))
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#define VCPU_USR_SP (VCPU_USR_REG(13))
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@ -420,6 +421,14 @@ vcpu .req r0 @ vcpu pointer always in r0
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ldr r8, [r2, #GICH_ELRSR0]
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ldr r9, [r2, #GICH_ELRSR1]
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ldr r10, [r2, #GICH_APR]
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ARM_BE8(rev r3, r3 )
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ARM_BE8(rev r4, r4 )
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ARM_BE8(rev r5, r5 )
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ARM_BE8(rev r6, r6 )
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ARM_BE8(rev r7, r7 )
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ARM_BE8(rev r8, r8 )
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ARM_BE8(rev r9, r9 )
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ARM_BE8(rev r10, r10 )
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str r3, [r11, #VGIC_V2_CPU_HCR]
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str r4, [r11, #VGIC_V2_CPU_VMCR]
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@ -439,6 +448,7 @@ vcpu .req r0 @ vcpu pointer always in r0
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add r3, r11, #VGIC_V2_CPU_LR
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ldr r4, [r11, #VGIC_CPU_NR_LR]
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1: ldr r6, [r2], #4
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ARM_BE8(rev r6, r6 )
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str r6, [r3], #4
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subs r4, r4, #1
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bne 1b
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@ -466,6 +476,9 @@ vcpu .req r0 @ vcpu pointer always in r0
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ldr r3, [r11, #VGIC_V2_CPU_HCR]
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ldr r4, [r11, #VGIC_V2_CPU_VMCR]
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ldr r8, [r11, #VGIC_V2_CPU_APR]
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ARM_BE8(rev r3, r3 )
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ARM_BE8(rev r4, r4 )
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ARM_BE8(rev r8, r8 )
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str r3, [r2, #GICH_HCR]
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str r4, [r2, #GICH_VMCR]
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@ -476,6 +489,7 @@ vcpu .req r0 @ vcpu pointer always in r0
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add r3, r11, #VGIC_V2_CPU_LR
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ldr r4, [r11, #VGIC_CPU_NR_LR]
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1: ldr r6, [r3], #4
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ARM_BE8(rev r6, r6 )
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str r6, [r2], #4
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subs r4, r4, #1
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bne 1b
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