ARM: tegra: Initialize pll_p_out1
pll_a uses pll_p_out1 as its parent. Therefore this clock needs to be initialized to make sure pll_a has a known input clock. Failure to do so will cause the system to crash early in the bootup. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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@ -93,6 +93,17 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
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};
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
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/* name parent rate enabled */
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{ "clk_m", NULL, 0, true },
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{ "pll_p", "clk_m", 408000000, true },
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{ "pll_p_out1", "pll_p", 9600000, true },
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{ NULL, NULL, 0, 0},
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};
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#endif
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static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
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{
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#ifdef CONFIG_CACHE_L2X0
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@ -127,6 +138,7 @@ void __init tegra30_init_early(void)
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{
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tegra_init_fuse();
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tegra30_init_clocks();
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tegra_clk_init_from_table(tegra30_clk_init_table);
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tegra_init_cache(0x441, 0x551);
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tegra_pmc_init();
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tegra_powergate_init();
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