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MIPS: Define some more PIIX4 registers & values 

This patch simply adds definitions for some I/O registers in the PIIX4
PM device, and the magic data for a special cycle which must occur on
the PCI bus in order for the PIIX4 to enter a suspend state.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6903/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
hifive-unleashed-5.1
Paul Burton 2014-05-07 12:20:56 +01:00 committed by Ralf Baechle
parent 76ad023b89
commit 643c5705bc
1 changed files with 12 additions and 0 deletions
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12
arch/mips/include/asm/mips-boards/piix4.h
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@ -55,4 +55,16 @@
#define PIIX4_FUNC3_PMREGMISC 0x80
#define PIIX4_FUNC3_PMREGMISC_EN (1 << 0)
/* Power Management IO Space */
#define PIIX4_FUNC3IO_PMSTS 0x00
#define PIIX4_FUNC3IO_PMSTS_PWRBTN_STS (1 << 8)
#define PIIX4_FUNC3IO_PMCNTRL 0x04
#define PIIX4_FUNC3IO_PMCNTRL_SUS_EN (1 << 13)
#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP (0x7 << 10)
#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF (0x0 << 10)
#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_STR (0x1 << 10)
/* Data for magic special PCI cycle */
#define PIIX4_SUSPEND_MAGIC 0x00120002
#endif /* __ASM_MIPS_BOARDS_PIIX4_H */