From 64424d6e45aeee311a4231def7e125bcc2de0855 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Sat, 6 Dec 2014 20:19:16 -0500 Subject: [PATCH] radeon/audio: consolidate update_acr() functions (v2) V2: fix missing dce6 callback Signed-off-by: Slava Grigorev Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/dce3_1_afmt.c | 38 ++++++- drivers/gpu/drm/radeon/evergreen_hdmi.c | 46 ++++----- drivers/gpu/drm/radeon/r600_hdmi.c | 129 +++++------------------- drivers/gpu/drm/radeon/radeon_audio.c | 100 ++++++++++++++++++ drivers/gpu/drm/radeon/radeon_audio.h | 3 + 5 files changed, 183 insertions(+), 133 deletions(-) diff --git a/drivers/gpu/drm/radeon/dce3_1_afmt.c b/drivers/gpu/drm/radeon/dce3_1_afmt.c index 0accc5ee0e39..2a963c173cc1 100644 --- a/drivers/gpu/drm/radeon/dce3_1_afmt.c +++ b/drivers/gpu/drm/radeon/dce3_1_afmt.c @@ -167,6 +167,38 @@ void dce3_2_audio_set_dto(struct radeon_device *rdev, } } +void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset, + const struct radeon_hdmi_acr *acr) +{ + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + + WREG32(HDMI0_ACR_PACKET_CONTROL + offset, + HDMI0_ACR_SOURCE | /* select SW CTS value */ + HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ + + WREG32_P(HDMI0_ACR_32_0 + offset, + HDMI0_ACR_CTS_32(acr->cts_32khz), + ~HDMI0_ACR_CTS_32_MASK); + WREG32_P(HDMI0_ACR_32_1 + offset, + HDMI0_ACR_N_32(acr->n_32khz), + ~HDMI0_ACR_N_32_MASK); + + WREG32_P(HDMI0_ACR_44_0 + offset, + HDMI0_ACR_CTS_44(acr->cts_44_1khz), + ~HDMI0_ACR_CTS_44_MASK); + WREG32_P(HDMI0_ACR_44_1 + offset, + HDMI0_ACR_N_44(acr->n_44_1khz), + ~HDMI0_ACR_N_44_MASK); + + WREG32_P(HDMI0_ACR_48_0 + offset, + HDMI0_ACR_CTS_48(acr->cts_48khz), + ~HDMI0_ACR_CTS_48_MASK); + WREG32_P(HDMI0_ACR_48_1 + offset, + HDMI0_ACR_N_48(acr->n_48khz), + ~HDMI0_ACR_N_48_MASK); +} + /* * update the info frames with the data from the current display mode */ @@ -220,10 +252,6 @@ void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *m radeon_audio_write_sad_regs(encoder); } - WREG32(HDMI0_ACR_PACKET_CONTROL + offset, - HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */ - HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ - WREG32(HDMI0_VBI_PACKET_CONTROL + offset, HDMI0_NULL_SEND | /* send null packets when required */ HDMI0_GC_SEND | /* send general control packets */ @@ -255,7 +283,7 @@ void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *m } radeon_update_avi_infoframe(encoder, buffer, sizeof(buffer)); - r600_hdmi_update_ACR(encoder, mode->clock); + radeon_audio_update_acr(encoder, mode->clock); /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index f2896e5ff055..05cef011c3af 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c @@ -64,26 +64,34 @@ void dce4_audio_enable(struct radeon_device *rdev, WREG32(AZ_HOT_PLUG_CONTROL, tmp); } -/* - * update the N and CTS parameters for a given pixel clock rate - */ -static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) +void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset, + const struct radeon_hdmi_acr *acr) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; - struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); - struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); - struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; - uint32_t offset = dig->afmt->offset; + int bpc = 8; - WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); - WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); + if (encoder->crtc) { + struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); + bpc = radeon_crtc->bpc; + } - WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); - WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); + if (bpc > 8) + WREG32(HDMI_ACR_PACKET_CONTROL + offset, + HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ + else + WREG32(HDMI_ACR_PACKET_CONTROL + offset, + HDMI_ACR_SOURCE | /* select SW CTS value */ + HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ - WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); - WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); + WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); + WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); + + WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); + WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); + + WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); + WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); } void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, @@ -378,15 +386,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ - if (bpc > 8) - WREG32(HDMI_ACR_PACKET_CONTROL + offset, - HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ - else - WREG32(HDMI_ACR_PACKET_CONTROL + offset, - HDMI_ACR_SOURCE | /* select SW CTS value */ - HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ - - evergreen_hdmi_update_ACR(encoder, mode->clock); + radeon_audio_update_acr(encoder, mode->clock); WREG32(AFMT_60958_0 + offset, AFMT_60958_CS_CHANNEL_NUMBER_L(1)); diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index 53ee7ad9612c..f91273912eb8 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c @@ -56,21 +56,6 @@ enum r600_hdmi_iec_status_bits { AUDIO_STATUS_LEVEL = 0x80 }; -static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { - /* 32kHz 44.1kHz 48kHz */ - /* Clock N CTS N CTS N CTS */ - { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */ - { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ - { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ - { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ - { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ - { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ - { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */ - { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ - { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */ - { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ -}; - static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev) { struct r600_audio_pin status; @@ -189,97 +174,41 @@ struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev) return &rdev->audio.pin[0]; } -/* - * calculate CTS and N values if they are not found in the table - */ -static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq) -{ - int n, cts; - unsigned long div, mul; - - /* Safe, but overly large values */ - n = 128 * freq; - cts = clock * 1000; - - /* Smallest valid fraction */ - div = gcd(n, cts); - - n /= div; - cts /= div; - - /* - * The optimal N is 128*freq/1000. Calculate the closest larger - * value that doesn't truncate any bits. - */ - mul = ((128*freq/1000) + (n-1))/n; - - n *= mul; - cts *= mul; - - /* Check that we are in spec (not always possible) */ - if (n < (128*freq/1500)) - printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n"); - if (n > (128*freq/300)) - printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n"); - - *N = n; - *CTS = cts; - - DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n", - *N, *CTS, freq); -} - -struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) -{ - struct radeon_hdmi_acr res; - u8 i; - - /* Precalculated values for common clocks */ - for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) { - if (r600_hdmi_predefined_acr[i].clock == clock) - return r600_hdmi_predefined_acr[i]; - } - - /* And odd clocks get manually calculated */ - r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); - r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); - r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); - - return res; -} - -/* - * update the N and CTS parameters for a given pixel clock rate - */ -void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) +void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset, + const struct radeon_hdmi_acr *acr) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; - struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); - struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); - struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; - uint32_t offset = dig->afmt->offset; + + /* DCE 3.0 uses register that's normally for CRC_CONTROL */ + uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL : + HDMI0_ACR_PACKET_CONTROL; + WREG32_P(acr_ctl + offset, + HDMI0_ACR_SOURCE | /* select SW CTS value */ + HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */ + ~(HDMI0_ACR_SOURCE | + HDMI0_ACR_AUTO_SEND)); WREG32_P(HDMI0_ACR_32_0 + offset, - HDMI0_ACR_CTS_32(acr.cts_32khz), - ~HDMI0_ACR_CTS_32_MASK); + HDMI0_ACR_CTS_32(acr->cts_32khz), + ~HDMI0_ACR_CTS_32_MASK); WREG32_P(HDMI0_ACR_32_1 + offset, - HDMI0_ACR_N_32(acr.n_32khz), - ~HDMI0_ACR_N_32_MASK); + HDMI0_ACR_N_32(acr->n_32khz), + ~HDMI0_ACR_N_32_MASK); WREG32_P(HDMI0_ACR_44_0 + offset, - HDMI0_ACR_CTS_44(acr.cts_44_1khz), - ~HDMI0_ACR_CTS_44_MASK); + HDMI0_ACR_CTS_44(acr->cts_44_1khz), + ~HDMI0_ACR_CTS_44_MASK); WREG32_P(HDMI0_ACR_44_1 + offset, - HDMI0_ACR_N_44(acr.n_44_1khz), - ~HDMI0_ACR_N_44_MASK); + HDMI0_ACR_N_44(acr->n_44_1khz), + ~HDMI0_ACR_N_44_MASK); WREG32_P(HDMI0_ACR_48_0 + offset, - HDMI0_ACR_CTS_48(acr.cts_48khz), - ~HDMI0_ACR_CTS_48_MASK); + HDMI0_ACR_CTS_48(acr->cts_48khz), + ~HDMI0_ACR_CTS_48_MASK); WREG32_P(HDMI0_ACR_48_1 + offset, - HDMI0_ACR_N_48(acr.n_48khz), - ~HDMI0_ACR_N_48_MASK); + HDMI0_ACR_N_48(acr->n_48khz), + ~HDMI0_ACR_N_48_MASK); } /* @@ -412,7 +341,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; struct hdmi_avi_infoframe frame; uint32_t offset; - uint32_t acr_ctl; ssize_t err; if (!dig || !dig->afmt) @@ -439,15 +367,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod HDMI0_AUDIO_PACKETS_PER_LINE_MASK | HDMI0_60958_CS_UPDATE)); - /* DCE 3.0 uses register that's normally for CRC_CONTROL */ - acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL : - HDMI0_ACR_PACKET_CONTROL; - WREG32_P(acr_ctl + offset, - HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */ - HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */ - ~(HDMI0_ACR_SOURCE | - HDMI0_ACR_AUTO_SEND)); - WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset, HDMI0_NULL_SEND | /* send null packets when required */ HDMI0_GC_SEND | /* send general control packets */ @@ -493,7 +412,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod HDMI0_GENERIC0_LINE_MASK | HDMI0_GENERIC1_LINE_MASK)); - r600_hdmi_update_ACR(encoder, mode->clock); + radeon_audio_update_acr(encoder, mode->clock); WREG32_P(HDMI0_60958_0 + offset, HDMI0_60958_CS_CHANNEL_NUMBER_L(1), diff --git a/drivers/gpu/drm/radeon/radeon_audio.c b/drivers/gpu/drm/radeon/radeon_audio.c index cc58ee8c7d2f..dbb3c594e9ae 100644 --- a/drivers/gpu/drm/radeon/radeon_audio.c +++ b/drivers/gpu/drm/radeon/radeon_audio.c @@ -22,6 +22,7 @@ * Authors: Slava Grigorev */ +#include #include #include #include "radeon.h" @@ -78,6 +79,12 @@ void r600_update_avi_infoframe(struct radeon_device *rdev, u32 offset, unsigned char *buffer, size_t size); void evergreen_update_avi_infoframe(struct radeon_device *rdev, u32 offset, unsigned char *buffer, size_t size); +void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset, + const struct radeon_hdmi_acr *acr); +void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset, + const struct radeon_hdmi_acr *acr); +void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset, + const struct radeon_hdmi_acr *acr); static const u32 pin_offsets[7] = { @@ -132,6 +139,7 @@ static struct radeon_audio_basic_funcs dce6_funcs = { static struct radeon_audio_funcs r600_hdmi_funcs = { .get_pin = r600_audio_get_pin, .set_dto = r600_hdmi_audio_set_dto, + .update_acr = r600_hdmi_update_acr, }; static struct radeon_audio_funcs dce32_hdmi_funcs = { @@ -139,6 +147,7 @@ static struct radeon_audio_funcs dce32_hdmi_funcs = { .write_sad_regs = dce3_2_afmt_write_sad_regs, .write_speaker_allocation = dce3_2_afmt_hdmi_write_speaker_allocation, .set_dto = dce3_2_audio_set_dto, + .update_acr = dce3_2_hdmi_update_acr, }; static struct radeon_audio_funcs dce32_dp_funcs = { @@ -154,6 +163,7 @@ static struct radeon_audio_funcs dce4_hdmi_funcs = { .write_speaker_allocation = dce4_afmt_hdmi_write_speaker_allocation, .write_latency_fields = dce4_afmt_write_latency_fields, .set_dto = dce4_hdmi_audio_set_dto, + .update_acr = evergreen_hdmi_update_acr, }; static struct radeon_audio_funcs dce4_dp_funcs = { @@ -171,6 +181,7 @@ static struct radeon_audio_funcs dce6_hdmi_funcs = { .write_speaker_allocation = dce6_afmt_hdmi_write_speaker_allocation, .write_latency_fields = dce6_afmt_write_latency_fields, .set_dto = dce6_hdmi_audio_set_dto, + .update_acr = evergreen_hdmi_update_acr, }; static struct radeon_audio_funcs dce6_dp_funcs = { @@ -456,3 +467,92 @@ void radeon_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, rdev->audio.funcs->update_avi_infoframe(rdev, dig->afmt->offset, buffer, size); } + +/* + * calculate CTS and N values if they are not found in the table + */ +static void radeon_audio_calc_cts(unsigned int clock, int *CTS, int *N, int freq) +{ + int n, cts; + unsigned long div, mul; + + /* Safe, but overly large values */ + n = 128 * freq; + cts = clock * 1000; + + /* Smallest valid fraction */ + div = gcd(n, cts); + + n /= div; + cts /= div; + + /* + * The optimal N is 128*freq/1000. Calculate the closest larger + * value that doesn't truncate any bits. + */ + mul = ((128*freq/1000) + (n-1))/n; + + n *= mul; + cts *= mul; + + /* Check that we are in spec (not always possible) */ + if (n < (128*freq/1500)) + printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n"); + if (n > (128*freq/300)) + printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n"); + + *N = n; + *CTS = cts; + + DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n", + *N, *CTS, freq); +} + +static const struct radeon_hdmi_acr* radeon_audio_acr(unsigned int clock) +{ + static struct radeon_hdmi_acr res; + u8 i; + + static const struct radeon_hdmi_acr hdmi_predefined_acr[] = { + /* 32kHz 44.1kHz 48kHz */ + /* Clock N CTS N CTS N CTS */ + { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */ + { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ + { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ + { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ + { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ + { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ + { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */ + { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ + { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */ + { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ + }; + + /* Precalculated values for common clocks */ + for (i = 0; i < ARRAY_SIZE(hdmi_predefined_acr); i++) + if (hdmi_predefined_acr[i].clock == clock) + return &hdmi_predefined_acr[i]; + + /* And odd clocks get manually calculated */ + radeon_audio_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); + radeon_audio_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); + radeon_audio_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); + + return &res; +} + +/* + * update the N and CTS parameters for a given pixel clock rate + */ +void radeon_audio_update_acr(struct drm_encoder *encoder, unsigned int clock) +{ + const struct radeon_hdmi_acr *acr = radeon_audio_acr(clock); + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; + + if (!dig || !dig->afmt) + return; + + if (radeon_encoder->audio && radeon_encoder->audio->update_acr) + radeon_encoder->audio->update_acr(encoder, dig->afmt->offset, acr); +} diff --git a/drivers/gpu/drm/radeon/radeon_audio.h b/drivers/gpu/drm/radeon/radeon_audio.h index dc85d53d1587..a4d055311ab5 100644 --- a/drivers/gpu/drm/radeon/radeon_audio.h +++ b/drivers/gpu/drm/radeon/radeon_audio.h @@ -55,6 +55,8 @@ struct radeon_audio_funcs u8 *sadb, int sad_count); void (*set_dto)(struct radeon_device *rdev, struct radeon_crtc *crtc, unsigned int clock); + void (*update_acr)(struct drm_encoder *encoder, long offset, + const struct radeon_hdmi_acr *acr); }; int radeon_audio_init(struct radeon_device *rdev); @@ -76,5 +78,6 @@ void radeon_audio_fini(struct radeon_device *rdev); void radeon_audio_set_dto(struct drm_encoder *encoder, unsigned int clock); void radeon_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, size_t size); +void radeon_audio_update_acr(struct drm_encoder *encoder, unsigned int clock); #endif