KVM: nVMX: Deciding if L0 or L1 should handle an L2 exit
This patch contains the logic of whether an L2 exit should be handled by L0 and then L2 should be resumed, or whether L1 should be run to handle this exit (using the nested_vmx_vmexit() function of the previous patch). The basic idea is to let L1 handle the exit only if it actually asked to trap this sort of event. For example, when L2 exits on a change to CR0, we check L1's CR0_GUEST_HOST_MASK to see if L1 expressed interest in any bit which changed; If it did, we exit to L1. But if it didn't it means that it is we (L0) that wished to trap this event, so we handle it ourselves. The next two patches add additional logic of what to do when an interrupt or exception is injected: Does L0 need to do it, should we exit to L1 to do it, or should we resume L2 and keep the exception to be injected later. We keep a new flag, "nested_run_pending", which can override the decision of which should run next, L1 or L2. nested_run_pending=1 means that we *must* run L2 next, not L1. This is necessary in particular when L1 did a VMLAUNCH of L2 and therefore expects L2 to be run (and perhaps be injected with an event it specified, etc.). Nested_run_pending is especially intended to avoid switching to L1 in the injection decision-point described above. Signed-off-by: Nadav Har'El <nyh@il.ibm.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>hifive-unleashed-5.1
Nadav Har'El
Avi Kivity
parent
7c1779384a
commit
644d711aa0
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@ -346,6 +346,8 @@ struct nested_vmx {
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struct list_head vmcs02_pool;
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int vmcs02_num;
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u64 vmcs01_tsc_offset;
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/* L2 must run next, and mustn't decide to exit to L1. */
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bool nested_run_pending;
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/*
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* Guest pages referred to in vmcs02 with host-physical pointers, so
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* we must keep them pinned while L2 runs.
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@ -865,6 +867,19 @@ static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
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(vmcs12->secondary_vm_exec_control & bit);
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}
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static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
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struct kvm_vcpu *vcpu)
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{
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return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
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}
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static inline bool is_exception(u32 intr_info)
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{
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return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
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== (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
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}
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static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
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static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
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struct vmcs12 *vmcs12,
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u32 reason, unsigned long qualification);
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@ -5277,6 +5292,229 @@ static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
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static const int kvm_vmx_max_exit_handlers =
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ARRAY_SIZE(kvm_vmx_exit_handlers);
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/*
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* Return 1 if we should exit from L2 to L1 to handle an MSR access access,
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* rather than handle it ourselves in L0. I.e., check whether L1 expressed
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* disinterest in the current event (read or write a specific MSR) by using an
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* MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
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*/
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static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
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struct vmcs12 *vmcs12, u32 exit_reason)
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{
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u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
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gpa_t bitmap;
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if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
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return 1;
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/*
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* The MSR_BITMAP page is divided into four 1024-byte bitmaps,
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* for the four combinations of read/write and low/high MSR numbers.
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* First we need to figure out which of the four to use:
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*/
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bitmap = vmcs12->msr_bitmap;
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if (exit_reason == EXIT_REASON_MSR_WRITE)
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bitmap += 2048;
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if (msr_index >= 0xc0000000) {
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msr_index -= 0xc0000000;
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bitmap += 1024;
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}
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/* Then read the msr_index'th bit from this bitmap: */
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if (msr_index < 1024*8) {
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unsigned char b;
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kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
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return 1 & (b >> (msr_index & 7));
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} else
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return 1; /* let L1 handle the wrong parameter */
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}
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/*
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* Return 1 if we should exit from L2 to L1 to handle a CR access exit,
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* rather than handle it ourselves in L0. I.e., check if L1 wanted to
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* intercept (via guest_host_mask etc.) the current event.
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*/
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static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
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struct vmcs12 *vmcs12)
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{
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unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
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int cr = exit_qualification & 15;
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int reg = (exit_qualification >> 8) & 15;
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unsigned long val = kvm_register_read(vcpu, reg);
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switch ((exit_qualification >> 4) & 3) {
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case 0: /* mov to cr */
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switch (cr) {
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case 0:
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if (vmcs12->cr0_guest_host_mask &
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(val ^ vmcs12->cr0_read_shadow))
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return 1;
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break;
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case 3:
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if ((vmcs12->cr3_target_count >= 1 &&
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vmcs12->cr3_target_value0 == val) ||
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(vmcs12->cr3_target_count >= 2 &&
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vmcs12->cr3_target_value1 == val) ||
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(vmcs12->cr3_target_count >= 3 &&
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vmcs12->cr3_target_value2 == val) ||
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(vmcs12->cr3_target_count >= 4 &&
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vmcs12->cr3_target_value3 == val))
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return 0;
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if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
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return 1;
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break;
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case 4:
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if (vmcs12->cr4_guest_host_mask &
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(vmcs12->cr4_read_shadow ^ val))
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return 1;
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break;
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case 8:
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if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
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return 1;
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break;
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}
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break;
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case 2: /* clts */
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if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
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(vmcs12->cr0_read_shadow & X86_CR0_TS))
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return 1;
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break;
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case 1: /* mov from cr */
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switch (cr) {
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case 3:
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if (vmcs12->cpu_based_vm_exec_control &
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CPU_BASED_CR3_STORE_EXITING)
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return 1;
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break;
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case 8:
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if (vmcs12->cpu_based_vm_exec_control &
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CPU_BASED_CR8_STORE_EXITING)
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return 1;
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break;
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}
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break;
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case 3: /* lmsw */
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/*
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* lmsw can change bits 1..3 of cr0, and only set bit 0 of
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* cr0. Other attempted changes are ignored, with no exit.
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*/
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if (vmcs12->cr0_guest_host_mask & 0xe &
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(val ^ vmcs12->cr0_read_shadow))
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return 1;
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if ((vmcs12->cr0_guest_host_mask & 0x1) &&
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!(vmcs12->cr0_read_shadow & 0x1) &&
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(val & 0x1))
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return 1;
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break;
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}
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return 0;
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}
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/*
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* Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
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* should handle it ourselves in L0 (and then continue L2). Only call this
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* when in is_guest_mode (L2).
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*/
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static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
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{
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u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
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u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
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if (vmx->nested.nested_run_pending)
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return 0;
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if (unlikely(vmx->fail)) {
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printk(KERN_INFO "%s failed vm entry %x\n",
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__func__, vmcs_read32(VM_INSTRUCTION_ERROR));
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return 1;
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}
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switch (exit_reason) {
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case EXIT_REASON_EXCEPTION_NMI:
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if (!is_exception(intr_info))
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return 0;
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else if (is_page_fault(intr_info))
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return enable_ept;
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return vmcs12->exception_bitmap &
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(1u << (intr_info & INTR_INFO_VECTOR_MASK));
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case EXIT_REASON_EXTERNAL_INTERRUPT:
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return 0;
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case EXIT_REASON_TRIPLE_FAULT:
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return 1;
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case EXIT_REASON_PENDING_INTERRUPT:
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case EXIT_REASON_NMI_WINDOW:
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/*
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* prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
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* (aka Interrupt Window Exiting) only when L1 turned it on,
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* so if we got a PENDING_INTERRUPT exit, this must be for L1.
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* Same for NMI Window Exiting.
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*/
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return 1;
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case EXIT_REASON_TASK_SWITCH:
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return 1;
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case EXIT_REASON_CPUID:
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return 1;
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case EXIT_REASON_HLT:
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return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
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case EXIT_REASON_INVD:
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return 1;
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case EXIT_REASON_INVLPG:
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return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
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case EXIT_REASON_RDPMC:
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return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
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case EXIT_REASON_RDTSC:
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return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
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case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
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case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
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case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
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case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
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case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
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/*
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* VMX instructions trap unconditionally. This allows L1 to
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* emulate them for its L2 guest, i.e., allows 3-level nesting!
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*/
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return 1;
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case EXIT_REASON_CR_ACCESS:
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return nested_vmx_exit_handled_cr(vcpu, vmcs12);
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case EXIT_REASON_DR_ACCESS:
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return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
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case EXIT_REASON_IO_INSTRUCTION:
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/* TODO: support IO bitmaps */
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return 1;
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case EXIT_REASON_MSR_READ:
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case EXIT_REASON_MSR_WRITE:
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return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
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case EXIT_REASON_INVALID_STATE:
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return 1;
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case EXIT_REASON_MWAIT_INSTRUCTION:
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return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
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case EXIT_REASON_MONITOR_INSTRUCTION:
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return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
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case EXIT_REASON_PAUSE_INSTRUCTION:
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return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
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nested_cpu_has2(vmcs12,
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SECONDARY_EXEC_PAUSE_LOOP_EXITING);
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case EXIT_REASON_MCE_DURING_VMENTRY:
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return 0;
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case EXIT_REASON_TPR_BELOW_THRESHOLD:
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return 1;
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case EXIT_REASON_APIC_ACCESS:
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return nested_cpu_has2(vmcs12,
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SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
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case EXIT_REASON_EPT_VIOLATION:
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case EXIT_REASON_EPT_MISCONFIG:
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return 0;
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case EXIT_REASON_WBINVD:
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return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
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case EXIT_REASON_XSETBV:
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return 1;
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default:
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return 1;
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}
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}
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static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
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{
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*info1 = vmcs_readl(EXIT_QUALIFICATION);
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@ -5299,6 +5537,17 @@ static int vmx_handle_exit(struct kvm_vcpu *vcpu)
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if (vmx->emulation_required && emulate_invalid_guest_state)
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return handle_invalid_guest_state(vcpu);
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if (exit_reason == EXIT_REASON_VMLAUNCH ||
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exit_reason == EXIT_REASON_VMRESUME)
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vmx->nested.nested_run_pending = 1;
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else
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vmx->nested.nested_run_pending = 0;
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if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
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nested_vmx_vmexit(vcpu);
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return 1;
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}
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if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
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vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
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vcpu->run->fail_entry.hardware_entry_failure_reason
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@ -5321,7 +5570,9 @@ static int vmx_handle_exit(struct kvm_vcpu *vcpu)
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"(0x%x) and exit reason is 0x%x\n",
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__func__, vectoring_info, exit_reason);
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if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
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if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
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!(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
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get_vmcs12(vcpu), vcpu)))) {
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if (vmx_interrupt_allowed(vcpu)) {
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vmx->soft_vnmi_blocked = 0;
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} else if (vmx->vnmi_blocked_time > 1000000000LL &&
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