drm/i915: split PCH clock gating init
Ibex Peak and CougarPoint already require a different setting (added here), and future chips will likely follow that precedent. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
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@ -210,6 +210,7 @@ struct drm_i915_display_funcs {
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struct drm_framebuffer *old_fb);
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struct drm_framebuffer *old_fb);
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void (*fdi_link_train)(struct drm_crtc *crtc);
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void (*fdi_link_train)(struct drm_crtc *crtc);
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void (*init_clock_gating)(struct drm_device *dev);
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void (*init_clock_gating)(struct drm_device *dev);
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void (*init_pch_clock_gating)(struct drm_device *dev);
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/* clock updates for mode set */
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/* clock updates for mode set */
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/* cursor updates */
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/* cursor updates */
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/* render clock increase/decrease */
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/* render clock increase/decrease */
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@ -3074,6 +3074,9 @@
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#define TRANS_6BPC (2<<5)
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#define TRANS_6BPC (2<<5)
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#define TRANS_12BPC (3<<5)
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#define TRANS_12BPC (3<<5)
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#define SOUTH_CHICKEN2 0xc2004
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#define DPLS_EDP_PPS_FIX_DIS (1<<0)
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#define _FDI_RXA_CHICKEN 0xc200c
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#define _FDI_RXA_CHICKEN 0xc200c
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#define _FDI_RXB_CHICKEN 0xc2010
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#define _FDI_RXB_CHICKEN 0xc2010
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#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
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#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
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@ -863,8 +863,7 @@ int i915_restore_state(struct drm_device *dev)
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I915_WRITE(IMR, dev_priv->saveIMR);
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I915_WRITE(IMR, dev_priv->saveIMR);
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}
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}
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/* Clock gating state */
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intel_init_clock_gating(dev);
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dev_priv->display.init_clock_gating(dev);
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if (IS_IRONLAKE_M(dev)) {
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if (IS_IRONLAKE_M(dev)) {
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ironlake_enable_drps(dev);
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ironlake_enable_drps(dev);
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@ -7231,13 +7231,6 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
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I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
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I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
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/*
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* On Ibex Peak and Cougar Point, we need to disable clock
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* gating for the panel power sequencer or it will fail to
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* start up when no ports are active.
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*/
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I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
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/*
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/*
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* According to the spec the following bits should be set in
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* According to the spec the following bits should be set in
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* order to enable memory self-refresh
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* order to enable memory self-refresh
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@ -7295,13 +7288,6 @@ static void gen6_init_clock_gating(struct drm_device *dev)
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I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
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I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
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/*
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* On Ibex Peak and Cougar Point, we need to disable clock
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* gating for the panel power sequencer or it will fail to
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* start up when no ports are active.
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*/
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I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
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I915_WRITE(ILK_DISPLAY_CHICKEN2,
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I915_WRITE(ILK_DISPLAY_CHICKEN2,
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I915_READ(ILK_DISPLAY_CHICKEN2) |
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I915_READ(ILK_DISPLAY_CHICKEN2) |
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ILK_ELPIN_409_SELECT);
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ILK_ELPIN_409_SELECT);
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@ -7344,13 +7330,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
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I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
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I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
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/*
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* On Ibex Peak and Cougar Point, we need to disable clock
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* gating for the panel power sequencer or it will fail to
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* start up when no ports are active.
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*/
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I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
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I915_WRITE(WM3_LP_ILK, 0);
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I915_WRITE(WM3_LP_ILK, 0);
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I915_WRITE(WM2_LP_ILK, 0);
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I915_WRITE(WM2_LP_ILK, 0);
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I915_WRITE(WM1_LP_ILK, 0);
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I915_WRITE(WM1_LP_ILK, 0);
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@ -7428,6 +7407,32 @@ static void i830_init_clock_gating(struct drm_device *dev)
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I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
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I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
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}
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}
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static void ibx_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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/*
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* On Ibex Peak and Cougar Point, we need to disable clock
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* gating for the panel power sequencer or it will fail to
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* start up when no ports are active.
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*/
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I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
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}
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static void cpt_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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/*
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* On Ibex Peak and Cougar Point, we need to disable clock
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* gating for the panel power sequencer or it will fail to
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* start up when no ports are active.
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*/
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I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
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I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
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DPLS_EDP_PPS_FIX_DIS);
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}
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static void ironlake_teardown_rc6(struct drm_device *dev)
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static void ironlake_teardown_rc6(struct drm_device *dev)
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{
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -7543,6 +7548,15 @@ void ironlake_enable_rc6(struct drm_device *dev)
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mutex_unlock(&dev->struct_mutex);
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mutex_unlock(&dev->struct_mutex);
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}
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}
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void intel_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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dev_priv->display.init_clock_gating(dev);
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if (dev_priv->display.init_pch_clock_gating)
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dev_priv->display.init_pch_clock_gating(dev);
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}
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/* Set up chip specific display functions */
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/* Set up chip specific display functions */
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static void intel_init_display(struct drm_device *dev)
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static void intel_init_display(struct drm_device *dev)
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@ -7600,6 +7614,11 @@ static void intel_init_display(struct drm_device *dev)
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/* For FIFO watermark updates */
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/* For FIFO watermark updates */
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if (HAS_PCH_SPLIT(dev)) {
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if (HAS_PCH_SPLIT(dev)) {
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if (HAS_PCH_IBX(dev))
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dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
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else if (HAS_PCH_CPT(dev))
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dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
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if (IS_GEN5(dev)) {
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if (IS_GEN5(dev)) {
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if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
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if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
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dev_priv->display.update_wm = ironlake_update_wm;
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dev_priv->display.update_wm = ironlake_update_wm;
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@ -7802,7 +7821,7 @@ void intel_modeset_init(struct drm_device *dev)
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i915_disable_vga(dev);
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i915_disable_vga(dev);
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intel_setup_outputs(dev);
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intel_setup_outputs(dev);
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dev_priv->display.init_clock_gating(dev);
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intel_init_clock_gating(dev);
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if (IS_IRONLAKE_M(dev)) {
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if (IS_IRONLAKE_M(dev)) {
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ironlake_enable_drps(dev);
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ironlake_enable_drps(dev);
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@ -344,4 +344,6 @@ extern int intel_overlay_attrs(struct drm_device *dev, void *data,
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extern void intel_fb_output_poll_changed(struct drm_device *dev);
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extern void intel_fb_output_poll_changed(struct drm_device *dev);
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extern void intel_fb_restore_mode(struct drm_device *dev);
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extern void intel_fb_restore_mode(struct drm_device *dev);
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extern void intel_init_clock_gating(struct drm_device *dev);
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#endif /* __INTEL_DRV_H__ */
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#endif /* __INTEL_DRV_H__ */
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