drm/gk104-/fb/ram: use parsed timing data in mr routines
All the other chipsets should be moved over to this too. It's not needed yet for the upcoming commits, so left this step as it'll conflict badly with Roy's GT21x reclocking work. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -40,7 +40,7 @@ nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts)
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int WL, CL, WR, at[2], dt, ds;
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int WL, CL, WR, at[2], dt, ds;
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int rq = ram->freq < 1000000; /* XXX */
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int rq = ram->freq < 1000000; /* XXX */
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switch (ram->ramcfg.version) {
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switch (ram->next->bios.ramcfg_ver) {
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case 0x11:
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case 0x11:
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pd = ram->next->bios.ramcfg_11_01_80;
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pd = ram->next->bios.ramcfg_11_01_80;
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lf = ram->next->bios.ramcfg_11_01_40;
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lf = ram->next->bios.ramcfg_11_01_40;
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@ -54,7 +54,7 @@ nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts)
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return -ENOSYS;
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return -ENOSYS;
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}
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}
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switch (ram->timing.version) {
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switch (ram->next->bios.timing_ver) {
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case 0x20:
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case 0x20:
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WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
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WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
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CL = (ram->next->bios.timing[1] & 0x0000001f);
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CL = (ram->next->bios.timing[1] & 0x0000001f);
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@ -72,8 +72,13 @@ nouveau_sddr3_calc(struct nouveau_ram *ram)
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{
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{
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struct nouveau_bios *bios = nouveau_bios(ram);
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struct nouveau_bios *bios = nouveau_bios(ram);
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int CWL, CL, WR, DLL = 0, ODT = 0;
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int CWL, CL, WR, DLL = 0, ODT = 0;
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u8 ver;
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switch (!!ram->timing.data * ram->timing.version) {
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ver = !!ram->timing.data * ram->timing.version;
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if (ram->next)
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ver = ram->next->bios.timing_ver;
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switch (ver) {
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case 0x10:
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case 0x10:
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if (ram->timing.size < 0x17) {
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if (ram->timing.size < 0x17) {
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/* XXX: NV50: Get CWL from the timing register */
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/* XXX: NV50: Get CWL from the timing register */
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@ -86,9 +91,9 @@ nouveau_sddr3_calc(struct nouveau_ram *ram)
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ODT = nv_ro08(bios, ram->timing.data + 0x0e) & 0x07;
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ODT = nv_ro08(bios, ram->timing.data + 0x0e) & 0x07;
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break;
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break;
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case 0x20:
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case 0x20:
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CWL = (nv_ro16(bios, ram->timing.data + 0x04) & 0x0f80) >> 7;
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CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
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CL = nv_ro08(bios, ram->timing.data + 0x04) & 0x1f;
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CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0;
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WR = nv_ro08(bios, ram->timing.data + 0x0a) & 0x7f;
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WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
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/* XXX: Get these values from the VBIOS instead */
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/* XXX: Get these values from the VBIOS instead */
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DLL = !(ram->mr[1] & 0x1);
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DLL = !(ram->mr[1] & 0x1);
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ODT = (ram->mr[1] & 0x004) >> 2 |
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ODT = (ram->mr[1] & 0x004) >> 2 |
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