drm/radeon: reset dma engine on gpu reset (v2)
This try to reset the dma engine when performing gpu reset. Hopefully bringing back the gpu dma engine in sane state. v2: agd5f: fix dma reset on cayman/TN, add support for SI Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
eaaa6983ab
commit
64c56e8ce3
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@ -2309,19 +2309,19 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin
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static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
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static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
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{
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{
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struct evergreen_mc_save save;
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struct evergreen_mc_save save;
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u32 grbm_reset = 0;
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u32 grbm_reset = 0, tmp;
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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return 0;
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return 0;
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dev_info(rdev->dev, "GPU softreset \n");
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dev_info(rdev->dev, "GPU softreset \n");
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
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RREG32(GRBM_STATUS));
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
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RREG32(GRBM_STATUS_SE0));
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dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
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RREG32(GRBM_STATUS_SE1));
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
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RREG32(SRBM_STATUS));
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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RREG32(CP_STALLED_STAT1));
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@ -2337,9 +2337,21 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
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if (evergreen_mc_wait_for_idle(rdev)) {
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if (evergreen_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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}
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/* Disable CP parsing/prefetching */
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/* Disable CP parsing/prefetching */
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
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/* Disable DMA */
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tmp = RREG32(DMA_RB_CNTL);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL, tmp);
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/* Reset dma */
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WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
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RREG32(SRBM_SOFT_RESET);
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udelay(50);
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WREG32(SRBM_SOFT_RESET, 0);
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/* reset all the gfx blocks */
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/* reset all the gfx blocks */
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grbm_reset = (SOFT_RESET_CP |
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grbm_reset = (SOFT_RESET_CP |
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SOFT_RESET_CB |
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SOFT_RESET_CB |
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@ -2362,13 +2374,13 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
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(void)RREG32(GRBM_SOFT_RESET);
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(void)RREG32(GRBM_SOFT_RESET);
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/* Wait a little for things to settle down */
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/* Wait a little for things to settle down */
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udelay(50);
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udelay(50);
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
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RREG32(GRBM_STATUS));
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
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RREG32(GRBM_STATUS_SE0));
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dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
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RREG32(GRBM_STATUS_SE1));
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
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RREG32(SRBM_STATUS));
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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RREG32(CP_STALLED_STAT1));
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@ -742,8 +742,9 @@
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#define SOFT_RESET_ROM (1 << 14)
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#define SOFT_RESET_ROM (1 << 14)
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#define SOFT_RESET_SEM (1 << 15)
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#define SOFT_RESET_SEM (1 << 15)
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#define SOFT_RESET_VMC (1 << 17)
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#define SOFT_RESET_VMC (1 << 17)
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#define SOFT_RESET_DMA (1 << 20)
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#define SOFT_RESET_TST (1 << 21)
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#define SOFT_RESET_TST (1 << 21)
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#define SOFT_RESET_REGBB (1 << 22)
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#define SOFT_RESET_REGBB (1 << 22)
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#define SOFT_RESET_ORB (1 << 23)
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#define SOFT_RESET_ORB (1 << 23)
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/* display watermarks */
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/* display watermarks */
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@ -2028,6 +2029,13 @@
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#define CAYMAN_PACKET3_DEALLOC_STATE 0x14
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#define CAYMAN_PACKET3_DEALLOC_STATE 0x14
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/* DMA regs common on r6xx/r7xx/evergreen/ni */
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/* DMA regs common on r6xx/r7xx/evergreen/ni */
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#define DMA_RB_CNTL 0xd000
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# define DMA_RB_ENABLE (1 << 0)
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# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
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# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
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# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
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# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
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# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
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#define DMA_STATUS_REG 0xd034
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#define DMA_STATUS_REG 0xd034
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#endif
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#endif
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@ -1309,19 +1309,19 @@ void cayman_dma_fini(struct radeon_device *rdev)
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static int cayman_gpu_soft_reset(struct radeon_device *rdev)
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static int cayman_gpu_soft_reset(struct radeon_device *rdev)
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{
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{
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struct evergreen_mc_save save;
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struct evergreen_mc_save save;
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u32 grbm_reset = 0;
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u32 grbm_reset = 0, tmp;
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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return 0;
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return 0;
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dev_info(rdev->dev, "GPU softreset \n");
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dev_info(rdev->dev, "GPU softreset \n");
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
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RREG32(GRBM_STATUS));
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
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RREG32(GRBM_STATUS_SE0));
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dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
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RREG32(GRBM_STATUS_SE1));
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
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RREG32(SRBM_STATUS));
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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RREG32(CP_STALLED_STAT1));
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@ -1346,9 +1346,26 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
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if (evergreen_mc_wait_for_idle(rdev)) {
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if (evergreen_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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}
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/* Disable CP parsing/prefetching */
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/* Disable CP parsing/prefetching */
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
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/* dma0 */
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tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
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/* dma1 */
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tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
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/* Reset dma */
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WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
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RREG32(SRBM_SOFT_RESET);
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udelay(50);
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WREG32(SRBM_SOFT_RESET, 0);
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/* reset all the gfx blocks */
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/* reset all the gfx blocks */
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grbm_reset = (SOFT_RESET_CP |
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grbm_reset = (SOFT_RESET_CP |
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SOFT_RESET_CB |
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SOFT_RESET_CB |
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@ -1373,13 +1390,13 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
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/* Wait a little for things to settle down */
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/* Wait a little for things to settle down */
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udelay(50);
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udelay(50);
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
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RREG32(GRBM_STATUS));
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
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RREG32(GRBM_STATUS_SE0));
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dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
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RREG32(GRBM_STATUS_SE1));
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
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RREG32(SRBM_STATUS));
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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RREG32(CP_STALLED_STAT1));
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@ -65,7 +65,7 @@
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#define SOFT_RESET_VMC (1 << 17)
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#define SOFT_RESET_VMC (1 << 17)
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#define SOFT_RESET_DMA (1 << 20)
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#define SOFT_RESET_DMA (1 << 20)
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#define SOFT_RESET_TST (1 << 21)
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#define SOFT_RESET_TST (1 << 21)
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#define SOFT_RESET_REGBB (1 << 22)
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#define SOFT_RESET_REGBB (1 << 22)
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#define SOFT_RESET_ORB (1 << 23)
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#define SOFT_RESET_ORB (1 << 23)
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#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
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#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
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@ -1283,11 +1283,11 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev)
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return 0;
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return 0;
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dev_info(rdev->dev, "GPU softreset \n");
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dev_info(rdev->dev, "GPU softreset \n");
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dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
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dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
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RREG32(R_008010_GRBM_STATUS));
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RREG32(R_008010_GRBM_STATUS));
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dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
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dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
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RREG32(R_008014_GRBM_STATUS2));
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RREG32(R_008014_GRBM_STATUS2));
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dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
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dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
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RREG32(R_000E50_SRBM_STATUS));
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RREG32(R_000E50_SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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RREG32(CP_STALLED_STAT1));
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@ -1303,8 +1303,24 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev)
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if (r600_mc_wait_for_idle(rdev)) {
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if (r600_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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}
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/* Disable CP parsing/prefetching */
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/* Disable CP parsing/prefetching */
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WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
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WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
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/* Disable DMA */
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tmp = RREG32(DMA_RB_CNTL);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL, tmp);
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/* Reset dma */
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if (rdev->family >= CHIP_RV770)
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WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
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else
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WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
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RREG32(SRBM_SOFT_RESET);
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udelay(50);
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WREG32(SRBM_SOFT_RESET, 0);
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/* Check if any of the rendering block is busy and reset it */
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/* Check if any of the rendering block is busy and reset it */
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if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
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if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
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(RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
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(RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
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@ -1336,11 +1352,11 @@ static int r600_gpu_soft_reset(struct radeon_device *rdev)
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WREG32(R_008020_GRBM_SOFT_RESET, 0);
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WREG32(R_008020_GRBM_SOFT_RESET, 0);
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/* Wait a little for things to settle down */
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/* Wait a little for things to settle down */
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mdelay(1);
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mdelay(1);
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dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
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dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
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RREG32(R_008010_GRBM_STATUS));
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RREG32(R_008010_GRBM_STATUS));
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dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
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dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
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RREG32(R_008014_GRBM_STATUS2));
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RREG32(R_008014_GRBM_STATUS2));
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dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
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dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
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RREG32(R_000E50_SRBM_STATUS));
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RREG32(R_000E50_SRBM_STATUS));
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
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RREG32(CP_STALLED_STAT1));
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RREG32(CP_STALLED_STAT1));
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@ -2129,7 +2129,7 @@ bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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static int si_gpu_soft_reset(struct radeon_device *rdev)
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static int si_gpu_soft_reset(struct radeon_device *rdev)
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{
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{
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struct evergreen_mc_save save;
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struct evergreen_mc_save save;
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u32 grbm_reset = 0;
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u32 grbm_reset = 0, tmp;
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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return 0;
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return 0;
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@ -2159,6 +2159,22 @@ static int si_gpu_soft_reset(struct radeon_device *rdev)
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/* Disable CP parsing/prefetching */
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/* Disable CP parsing/prefetching */
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
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/* dma0 */
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tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
|
||||||
|
|
||||||
|
/* dma1 */
|
||||||
|
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
|
||||||
|
tmp &= ~DMA_RB_ENABLE;
|
||||||
|
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
|
||||||
|
|
||||||
|
/* Reset dma */
|
||||||
|
WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
|
||||||
|
RREG32(SRBM_SOFT_RESET);
|
||||||
|
udelay(50);
|
||||||
|
WREG32(SRBM_SOFT_RESET, 0);
|
||||||
|
|
||||||
/* reset all the gfx blocks */
|
/* reset all the gfx blocks */
|
||||||
grbm_reset = (SOFT_RESET_CP |
|
grbm_reset = (SOFT_RESET_CP |
|
||||||
SOFT_RESET_CB |
|
SOFT_RESET_CB |
|
||||||
|
|
|
@ -62,6 +62,22 @@
|
||||||
|
|
||||||
#define SRBM_STATUS 0xE50
|
#define SRBM_STATUS 0xE50
|
||||||
|
|
||||||
|
#define SRBM_SOFT_RESET 0x0E60
|
||||||
|
#define SOFT_RESET_BIF (1 << 1)
|
||||||
|
#define SOFT_RESET_DC (1 << 5)
|
||||||
|
#define SOFT_RESET_DMA1 (1 << 6)
|
||||||
|
#define SOFT_RESET_GRBM (1 << 8)
|
||||||
|
#define SOFT_RESET_HDP (1 << 9)
|
||||||
|
#define SOFT_RESET_IH (1 << 10)
|
||||||
|
#define SOFT_RESET_MC (1 << 11)
|
||||||
|
#define SOFT_RESET_ROM (1 << 14)
|
||||||
|
#define SOFT_RESET_SEM (1 << 15)
|
||||||
|
#define SOFT_RESET_VMC (1 << 17)
|
||||||
|
#define SOFT_RESET_DMA (1 << 20)
|
||||||
|
#define SOFT_RESET_TST (1 << 21)
|
||||||
|
#define SOFT_RESET_REGBB (1 << 22)
|
||||||
|
#define SOFT_RESET_ORB (1 << 23)
|
||||||
|
|
||||||
#define CC_SYS_RB_BACKEND_DISABLE 0xe80
|
#define CC_SYS_RB_BACKEND_DISABLE 0xe80
|
||||||
#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
|
#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue