Merge tag 'mvebu-dt-3.15-4' of git://git.infradead.org/linux-mvebu into next/dt
Merge "mvebu dt changes for v3.15 (incremental #4)" from Jason Cooper: - dove - add system controller node - drop pinctrl PMU reg property _before_ it hits mainline and becomes ABI - mvebu - XP/370 - change default PCIe apertures - switch GP and DB boards internal registers to 0xf1000000 - correct RAM size on Matrix board - 385 - correct phy connection type for DB board - add RD board * tag 'mvebu-dt-3.15-4' of git://git.infradead.org/linux-mvebu: ARM: dove: drop pinctrl PMU reg property ARM: mvebu: add Device Tree for the Armada 385 RD board ARM: mvebu: use the correct phy connection mode on Armada 385 DB ARM: mvebu: the Armada XP Matrix board has 4 GB ARM: mvebu: switch the Armada XP GP to use internal registers at 0xf1000000 ARM: mvebu: switch the Armada XP DB to use internal registers at 0xf1000000 ARM: mvebu: change the default PCIe apertures for Armada 370/XP ARM: dove: add system controller node Conflicts: arch/arm/boot/dts/Makefile Signed-off-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
Arnd Bergmann
commit
64d865f403
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@ -55,11 +55,6 @@ dtb-$(CONFIG_ARCH_BERLIN) += \
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berlin2cd-google-chromecast.dtb
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dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
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da850-evm.dtb
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dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
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dove-cubox.dtb \
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dove-d2plug.dtb \
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dove-d3plug.dtb \
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dove-dove-db.dtb
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dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
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dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
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exynos4210-smdkv310.dtb \
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@ -378,7 +373,8 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
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dtb-$(CONFIG_MACH_ARMADA_375) += \
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armada-375-db.dtb
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dtb-$(CONFIG_MACH_ARMADA_38X) += \
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armada-385-db.dtb
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armada-385-db.dtb \
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armada-385-rd.dtb
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dtb-$(CONFIG_MACH_ARMADA_XP) += \
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armada-xp-axpwifiap.dtb \
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armada-xp-db.dtb \
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@ -386,6 +382,11 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \
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armada-xp-netgear-rn2120.dtb \
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armada-xp-matrix.dtb \
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armada-xp-openblocks-ax3-4.dtb
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dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
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dove-cubox.dtb \
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dove-d2plug.dtb \
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dove-d3plug.dtb \
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dove-dove-db.dtb
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targets += dtbs
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targets += $(dtb-y)
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@ -44,8 +44,8 @@
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#size-cells = <1>;
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controller = <&mbusc>;
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interrupt-parent = <&mpic>;
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pcie-mem-aperture = <0xe0000000 0x8000000>;
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pcie-io-aperture = <0xe8000000 0x100000>;
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pcie-mem-aperture = <0xf8000000 0x7e00000>;
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pcie-io-aperture = <0xffe00000 0x100000>;
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devbus-bootcs {
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compatible = "marvell,mvebu-devbus";
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@ -62,13 +62,13 @@
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ethernet@30000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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};
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ethernet@70000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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};
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mdio {
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@ -0,0 +1,94 @@
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/*
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* Device Tree file for Marvell Armada 385 Reference Design board
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* (RD-88F6820-AP)
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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#include "armada-385.dtsi"
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/ {
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model = "Marvell Armada 385 Reference Design";
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compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x";
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chosen {
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bootargs = "console=ttyS0,115200 earlyprintk";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; /* 256 MB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
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internal-regs {
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spi@10600 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p128";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <108000000>;
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};
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};
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i2c@11000 {
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status = "okay";
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clock-frequency = <100000>;
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};
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serial@12000 {
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clock-frequency = <200000000>;
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status = "okay";
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};
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ethernet@30000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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ethernet@70000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* One PCIe units is accessible through
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* standard PCIe slot on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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};
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};
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};
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@ -2,7 +2,7 @@
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* Device Tree file for Marvell Armada XP evaluation board
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* (DB-78460-BP)
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*
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* Copyright (C) 2012 Marvell
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* Copyright (C) 2012-2014 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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@ -11,6 +11,15 @@
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Note: this Device Tree assumes that the bootloader has remapped the
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* internal registers to 0xf1000000 (instead of the default
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* 0xd0000000). The 0xf1000000 is the default used by the recent,
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* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
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* boards were delivered with an older version of the bootloader that
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* left internal registers mapped at 0xd0000000. If you are in this
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* situation, you should either update your bootloader (preferred
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* solution) or the below Device Tree should be adjusted.
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*/
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/dts-v1/;
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@ -30,7 +39,7 @@
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
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@ -2,7 +2,7 @@
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* Device Tree file for Marvell Armada XP development board
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* (DB-MV784MP-GP)
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*
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* Copyright (C) 2013 Marvell
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* Copyright (C) 2013-2014 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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@ -11,6 +11,15 @@
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Note: this Device Tree assumes that the bootloader has remapped the
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* internal registers to 0xf1000000 (instead of the default
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* 0xd0000000). The 0xf1000000 is the default used by the recent,
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* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
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* boards were delivered with an older version of the bootloader that
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* left internal registers mapped at 0xd0000000. If you are in this
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* situation, you should either update your bootloader (preferred
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* solution) or the below Device Tree should be adjusted.
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*/
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/dts-v1/;
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@ -30,16 +39,17 @@
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* 8 GB of plug-in RAM modules by default.The amount
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* of memory available can be changed by the
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* bootloader according the size of the module
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* actually plugged. Only 7GB are usable because
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* addresses from 0xC0000000 to 0xffffffff are used by
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* the internal registers of the SoC.
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* actually plugged. However, memory between
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* 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
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* the address range used for I/O (internal registers,
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* MBus windows).
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*/
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reg = <0x00000000 0x00000000 0x00000000 0xC0000000>,
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reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
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<0x00000001 0x00000000 0x00000001 0x00000000>;
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
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@ -23,7 +23,12 @@
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memory {
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device_type = "memory";
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reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
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/*
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* This board has 4 GB of RAM, but the last 256 MB of
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* RAM are not usable due to the overlap with the MBus
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* Window address range
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*/
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reg = <0 0x00000000 0 0xf0000000>;
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};
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soc {
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@ -186,6 +186,11 @@
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reg = <0x20000 0x80>, <0x800100 0x8>;
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};
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sysc: system-ctrl@20000 {
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compatible = "marvell,orion-system-controller";
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reg = <0x20000 0x110>;
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};
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bridge_intc: bridge-interrupt-ctrl@20110 {
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compatible = "marvell,orion-bridge-intc";
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interrupt-controller;
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@ -390,8 +395,7 @@
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pinctrl: pin-ctrl@d0200 {
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compatible = "marvell,dove-pinctrl";
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reg = <0xd0200 0x14>,
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<0xd0440 0x04>,
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<0xd802c 0x08>;
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<0xd0440 0x04>;
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clocks = <&gate_clk 22>;
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pmx_gpio_0: pmx-gpio-0 {
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