drm/i915: Clear lost context-switch interrupts across reset
During a global reset, we disable the irq. As we disable the irq, the
hardware may be raising a GT interrupt that we then ignore, leaving it
pending in the GTIIR. After the reset, we then re-enable the irq,
triggering the pending interrupt. However, that interrupt was for the
stale state from before the reset, and the contents of the CSB buffer
are now invalid.
v2: Add a comment to make it clear that the double clear is purely my
paranoia.
Reported-by: "Dong, Chuanxiao" <chuanxiao.dong@intel.com>
Fixes: 821ed7df6e
("drm/i915: Update reset path to fix incomplete requests")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Dong, Chuanxiao" <chuanxiao.dong@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Winiarski <michal.winiarski@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170807121919.30165-1-chris@chris-wilson.co.uk
Link: https://patchwork.freedesktop.org/patch/msgid/20170818090509.5363-1-chris@chris-wilson.co.uk
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
This commit is contained in:
parent
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@ -1221,6 +1221,14 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
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return ret;
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return ret;
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}
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}
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static u8 gtiir[] = {
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[RCS] = 0,
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[BCS] = 0,
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[VCS] = 1,
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[VCS2] = 1,
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[VECS] = 3,
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};
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static int gen8_init_common_ring(struct intel_engine_cs *engine)
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static int gen8_init_common_ring(struct intel_engine_cs *engine)
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{
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct drm_i915_private *dev_priv = engine->i915;
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@ -1245,9 +1253,22 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
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DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
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DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
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/* After a GPU reset, we may have requests to replay */
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GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
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/*
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* Clear any pending interrupt state.
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*
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* We do it twice out of paranoia that some of the IIR are double
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* buffered, and if we only reset it once there may still be
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* an interrupt pending.
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*/
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I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
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GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
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I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
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GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
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clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
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clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
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/* After a GPU reset, we may have requests to replay */
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submit = false;
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submit = false;
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for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
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for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
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if (!port_isset(&port[n]))
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if (!port_isset(&port[n]))
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