tg3: Add memory barriers to sync BD data
for weak memory model architectures to ensure that the chip will DMA valid BD data. Signed-off-by: Michael Chan <mchan@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Reviewed-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -5928,6 +5928,9 @@ next_pkt_nopost:
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/* Refill RX ring(s). */
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if (!tg3_flag(tp, ENABLE_RSS)) {
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/* Sync BD data before updating mailbox */
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wmb();
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if (work_mask & RXD_OPAQUE_RING_STD) {
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tpr->rx_std_prod_idx = std_prod_idx &
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tp->rx_std_ring_mask;
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@ -6970,6 +6973,9 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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skb_tx_timestamp(skb);
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netdev_sent_queue(tp->dev, skb->len);
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/* Sync BD data before updating mailbox */
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wmb();
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/* Packets are ready, update Tx producer idx local and on card. */
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tw32_tx_mbox(tnapi->prodmbox, entry);
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@ -11763,6 +11769,9 @@ static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
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tnapi->tx_prod++;
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/* Sync BD data before updating mailbox */
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wmb();
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tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
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tr32_mailbox(tnapi->prodmbox);
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