tg3: Add memory barriers to sync BD data

for weak memory model architectures to ensure that the chip will DMA
valid BD data.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Reviewed-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan 2012-03-04 14:48:14 +00:00 committed by David S. Miller
parent c441b45676
commit 6541b806b5

View file

@ -5928,6 +5928,9 @@ next_pkt_nopost:
/* Refill RX ring(s). */
if (!tg3_flag(tp, ENABLE_RSS)) {
/* Sync BD data before updating mailbox */
wmb();
if (work_mask & RXD_OPAQUE_RING_STD) {
tpr->rx_std_prod_idx = std_prod_idx &
tp->rx_std_ring_mask;
@ -6970,6 +6973,9 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
skb_tx_timestamp(skb);
netdev_sent_queue(tp->dev, skb->len);
/* Sync BD data before updating mailbox */
wmb();
/* Packets are ready, update Tx producer idx local and on card. */
tw32_tx_mbox(tnapi->prodmbox, entry);
@ -11763,6 +11769,9 @@ static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
tnapi->tx_prod++;
/* Sync BD data before updating mailbox */
wmb();
tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
tr32_mailbox(tnapi->prodmbox);