redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

ARM: dts: omap3 clock data 

This patch creates a unique node for each clock in the OMAP3 power,
reset and clock manager (PRCM).

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
hifive-unleashed-5.1
Tero Kristo 2013-07-22 12:29:29 +03:00 committed by Mike Turquette
parent ea291c9851
commit 657fc11cca
10 changed files with 2844 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

128
arch/arm/boot/dts/am35xx-clocks.dtsi 100644
View File

@ -0,0 +1,128 @@
/*
* Device Tree Source for OMAP3 clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
emac_ick: emac_ick {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
reg = <0x059c>;
ti,bit-shift = <1>;
};
emac_fck: emac_fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&rmii_ck>;
reg = <0x059c>;
ti,bit-shift = <9>;
};
vpfe_ick: vpfe_ick {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
reg = <0x059c>;
ti,bit-shift = <2>;
};
vpfe_fck: vpfe_fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&pclk_ck>;
reg = <0x059c>;
ti,bit-shift = <10>;
};
hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
reg = <0x059c>;
ti,bit-shift = <0>;
};
hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_ck>;
reg = <0x059c>;
ti,bit-shift = <8>;
};
hecc_ck: hecc_ck {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&sys_ck>;
reg = <0x059c>;
ti,bit-shift = <3>;
};
};
&cm_clocks {
ipss_ick: ipss_ick {
#clock-cells = <0>;
compatible = "ti,am35xx-interface-clock";
clocks = <&core_l3_ick>;
reg = <0x0a10>;
ti,bit-shift = <4>;
};
rmii_ck: rmii_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
pclk_ck: pclk_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <27000000>;
};
uart4_ick_am35xx: uart4_ick_am35xx {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <23>;
};
uart4_fck_am35xx: uart4_fck_am35xx {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
reg = <0x0a00>;
ti,bit-shift = <23>;
};
};
&cm_clockdomains {
core_l3_clkdm: core_l3_clkdm {
compatible = "ti,clockdomain";
clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
<&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
<&hecc_ck>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
<&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
};
};

41
arch/arm/boot/dts/omap3.dtsi
View File

@ -89,6 +89,45 @@
interrupts = <0>;
};
prm: prm@48306000 {
compatible = "ti,omap3-prm";
reg = <0x48306000 0x4000>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
cm: cm@48004000 {
compatible = "ti,omap3-cm";
reg = <0x48004000 0x4000>;
cm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_clockdomains: clockdomains {
};
};
scrm: scrm@48002000 {
compatible = "ti,omap3-scrm";
reg = <0x48002000 0x2000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
counter32k: counter@48320000 {
compatible = "ti,omap-counter32k";
reg = <0x48320000 0x20>;
@ -632,3 +671,5 @@
};
};
};
/include/ "omap3xxx-clocks.dtsi"

208
arch/arm/boot/dts/omap3430es1-clocks.dtsi 100644
View File

@ -0,0 +1,208 @@
/*
* Device Tree Source for OMAP3430 ES1 clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&cm_clocks {
gfx_l3_ck: gfx_l3_ck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&l3_ick>;
reg = <0x0b10>;
ti,bit-shift = <0>;
};
gfx_l3_fck: gfx_l3_fck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&l3_ick>;
ti,max-div = <7>;
reg = <0x0b40>;
ti,index-starts-at-one;
};
gfx_l3_ick: gfx_l3_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&gfx_l3_ck>;
clock-mult = <1>;
clock-div = <1>;
};
gfx_cg1_ck: gfx_cg1_ck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&gfx_l3_fck>;
reg = <0x0b00>;
ti,bit-shift = <1>;
};
gfx_cg2_ck: gfx_cg2_ck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&gfx_l3_fck>;
reg = <0x0b00>;
ti,bit-shift = <2>;
};
d2d_26m_fck: d2d_26m_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&sys_ck>;
reg = <0x0a00>;
ti,bit-shift = <3>;
};
fshostusb_fck: fshostusb_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
reg = <0x0a00>;
ti,bit-shift = <5>;
};
ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&corex2_fck>;
ti,bit-shift = <0>;
reg = <0x0a00>;
};
ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&corex2_fck>;
ti,bit-shift = <8>;
reg = <0x0a40>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};
ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
};
ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&ssi_ssr_fck_3430es1>;
clock-mult = <1>;
clock-div = <2>;
};
hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&core_l3_ick>;
reg = <0x0a10>;
ti,bit-shift = <4>;
};
fac_ick: fac_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <8>;
};
ssi_l4_ick: ssi_l4_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l4_ick>;
clock-mult = <1>;
clock-div = <1>;
};
ssi_ick_3430es1: ssi_ick_3430es1 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&ssi_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <0>;
};
usb_l4_gate_ick: usb_l4_gate_ick {
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clocks = <&l4_ick>;
ti,bit-shift = <5>;
reg = <0x0a10>;
};
usb_l4_div_ick: usb_l4_div_ick {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&l4_ick>;
ti,bit-shift = <4>;
ti,max-div = <1>;
reg = <0x0a40>;
ti,index-starts-at-one;
};
usb_l4_ick: usb_l4_ick {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
};
dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m4x2_ck>;
ti,bit-shift = <0>;
reg = <0x0e00>;
ti,set-rate-parent;
};
dss_ick_3430es1: dss_ick_3430es1 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&l4_ick>;
reg = <0x0e10>;
ti,bit-shift = <0>;
};
};
&cm_clockdomains {
core_l3_clkdm: core_l3_clkdm {
compatible = "ti,clockdomain";
clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
};
gfx_3430es1_clkdm: gfx_3430es1_clkdm {
compatible = "ti,clockdomain";
clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
};
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
<&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;
};
d2d_clkdm: d2d_clkdm {
compatible = "ti,clockdomain";
clocks = <&d2d_26m_fck>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
<&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>;
};
};

268
arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi 100644
View File

@ -0,0 +1,268 @@
/*
* Device Tree Source for OMAP34XX/OMAP36XX clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&cm_clocks {
security_l4_ick2: security_l4_ick2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l4_ick>;
clock-mult = <1>;
clock-div = <1>;
};
aes1_ick: aes1_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
ti,bit-shift = <3>;
reg = <0x0a14>;
};
rng_ick: rng_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
reg = <0x0a14>;
ti,bit-shift = <2>;
};
sha11_ick: sha11_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
reg = <0x0a14>;
ti,bit-shift = <1>;
};
des1_ick: des1_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
reg = <0x0a14>;
ti,bit-shift = <0>;
};
cam_mclk: cam_mclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m5x2_ck>;
ti,bit-shift = <0>;
reg = <0x0f00>;
ti,set-rate-parent;
};
cam_ick: cam_ick {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&l4_ick>;
reg = <0x0f10>;
ti,bit-shift = <0>;
};
csi2_96m_fck: csi2_96m_fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&core_96m_fck>;
reg = <0x0f00>;
ti,bit-shift = <1>;
};
security_l3_ick: security_l3_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l3_ick>;
clock-mult = <1>;
clock-div = <1>;
};
pka_ick: pka_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l3_ick>;
reg = <0x0a14>;
ti,bit-shift = <4>;
};
icr_ick: icr_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <29>;
};
des2_ick: des2_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <26>;
};
mspro_ick: mspro_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <23>;
};
mailboxes_ick: mailboxes_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <7>;
};
ssi_l4_ick: ssi_l4_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l4_ick>;
clock-mult = <1>;
clock-div = <1>;
};
sr1_fck: sr1_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&sys_ck>;
reg = <0x0c00>;
ti,bit-shift = <6>;
};
sr2_fck: sr2_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&sys_ck>;
reg = <0x0c00>;
ti,bit-shift = <7>;
};
sr_l4_ick: sr_l4_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l4_ick>;
clock-mult = <1>;
clock-div = <1>;
};
dpll2_fck: dpll2_fck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&core_ck>;
ti,bit-shift = <19>;
ti,max-div = <7>;
reg = <0x0040>;
ti,index-starts-at-one;
};
dpll2_ck: dpll2_ck {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-clock";
clocks = <&sys_ck>, <&dpll2_fck>;
reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
ti,low-power-stop;
ti,lock;
ti,low-power-bypass;
};
dpll2_m2_ck: dpll2_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll2_ck>;
ti,max-div = <31>;
reg = <0x0044>;
ti,index-starts-at-one;
};
iva2_ck: iva2_ck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&dpll2_m2_ck>;
reg = <0x0000>;
ti,bit-shift = <0>;
};
modem_fck: modem_fck {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
reg = <0x0a00>;
ti,bit-shift = <31>;
};
sad2d_ick: sad2d_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l3_ick>;
reg = <0x0a10>;
ti,bit-shift = <3>;
};
mad2d_ick: mad2d_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l3_ick>;
reg = <0x0a18>;
ti,bit-shift = <3>;
};
mspro_fck: mspro_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;
reg = <0x0a00>;
ti,bit-shift = <23>;
};
};
&cm_clockdomains {
cam_clkdm: cam_clkdm {
compatible = "ti,clockdomain";
clocks = <&cam_ick>, <&csi2_96m_fck>;
};
iva2_clkdm: iva2_clkdm {
compatible = "ti,clockdomain";
clocks = <&iva2_ck>;
};
dpll2_clkdm: dpll2_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll2_ck>;
};
wkup_clkdm: wkup_clkdm {
compatible = "ti,clockdomain";
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
<&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
};
d2d_clkdm: d2d_clkdm {
compatible = "ti,clockdomain";
clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
<&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
<&mspro_fck>;
};
};

4
arch/arm/boot/dts/omap34xx.dtsi
View File

@ -26,3 +26,7 @@
};
};
};
/include/ "omap34xx-omap36xx-clocks.dtsi"
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

242
arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi 100644
View File

@ -0,0 +1,242 @@
/*
* Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&prm_clocks {
corex2_d3_fck: corex2_d3_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&corex2_fck>;
clock-mult = <1>;
clock-div = <3>;
};
corex2_d5_fck: corex2_d5_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&corex2_fck>;
clock-mult = <1>;
clock-div = <5>;
};
};
&cm_clocks {
dpll5_ck: dpll5_ck {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-clock";
clocks = <&sys_ck>, <&sys_ck>;
reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
ti,low-power-stop;
ti,lock;
};
dpll5_m2_ck: dpll5_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll5_ck>;
ti,max-div = <31>;
reg = <0x0d50>;
ti,index-starts-at-one;
};
sgx_gate_fck: sgx_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_ck>;
ti,bit-shift = <1>;
reg = <0x0b00>;
};
core_d3_ck: core_d3_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&core_ck>;
clock-mult = <1>;
clock-div = <3>;
};
core_d4_ck: core_d4_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&core_ck>;
clock-mult = <1>;
clock-div = <4>;
};
core_d6_ck: core_d6_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&core_ck>;
clock-mult = <1>;
clock-div = <6>;
};
omap_192m_alwon_fck: omap_192m_alwon_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll4_m2x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
core_d2_ck: core_d2_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&core_ck>;
clock-mult = <1>;
clock-div = <2>;
};
sgx_mux_fck: sgx_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
reg = <0x0b40>;
};
sgx_fck: sgx_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
};
sgx_ick: sgx_ick {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&l3_ick>;
reg = <0x0b10>;
ti,bit-shift = <0>;
};
cpefuse_fck: cpefuse_fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_ck>;
reg = <0x0a08>;
ti,bit-shift = <0>;
};
ts_fck: ts_fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&omap_32k_fck>;
reg = <0x0a08>;
ti,bit-shift = <1>;
};
usbtll_fck: usbtll_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&dpll5_m2_ck>;
reg = <0x0a08>;
ti,bit-shift = <2>;
};
usbtll_ick: usbtll_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a18>;
ti,bit-shift = <2>;
};
mmchs3_ick: mmchs3_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <30>;
};
mmchs3_fck: mmchs3_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;
reg = <0x0a00>;
ti,bit-shift = <30>;
};
dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 {
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clocks = <&dpll4_m4x2_ck>;
ti,bit-shift = <0>;
reg = <0x0e00>;
ti,set-rate-parent;
};
dss_ick_3430es2: dss_ick_3430es2 {
#clock-cells = <0>;
compatible = "ti,omap3-dss-interface-clock";
clocks = <&l4_ick>;
reg = <0x0e10>;
ti,bit-shift = <0>;
};
usbhost_120m_fck: usbhost_120m_fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll5_m2_ck>;
reg = <0x1400>;
ti,bit-shift = <1>;
};
usbhost_48m_fck: usbhost_48m_fck {
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clocks = <&omap_48m_fck>;
reg = <0x1400>;
ti,bit-shift = <0>;
};
usbhost_ick: usbhost_ick {
#clock-cells = <0>;
compatible = "ti,omap3-dss-interface-clock";
clocks = <&l4_ick>;
reg = <0x1410>;
ti,bit-shift = <0>;
};
};
&cm_clockdomains {
dpll5_clkdm: dpll5_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll5_ck>;
};
sgx_clkdm: sgx_clkdm {
compatible = "ti,clockdomain";
clocks = <&sgx_ick>;
};
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
<&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
<&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
};
usbhost_clkdm: usbhost_clkdm {
compatible = "ti,clockdomain";
clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
<&usbhost_ick>;
};
};

90
arch/arm/boot/dts/omap36xx-clocks.dtsi 100644
View File

@ -0,0 +1,90 @@
/*
* Device Tree Source for OMAP36xx clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&cm_clocks {
dpll4_ck: dpll4_ck {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-per-j-type-clock";
clocks = <&sys_ck>, <&sys_ck>;
reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
};
dpll4_m5x2_ck: dpll4_m5x2_ck {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m5x2_mul_ck>;
ti,bit-shift = <0x1e>;
reg = <0x0d00>;
ti,set-rate-parent;
ti,set-bit-to-disable;
};
dpll4_m2x2_ck: dpll4_m2x2_ck {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m2x2_mul_ck>;
ti,bit-shift = <0x1b>;
reg = <0x0d00>;
ti,set-bit-to-disable;
};
dpll3_m3x2_ck: dpll3_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll3_m3x2_mul_ck>;
ti,bit-shift = <0xc>;
reg = <0x0d00>;
ti,set-bit-to-disable;
};
dpll4_m3x2_ck: dpll4_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m3x2_mul_ck>;
ti,bit-shift = <0x1c>;
reg = <0x0d00>;
ti,set-bit-to-disable;
};
dpll4_m6x2_ck: dpll4_m6x2_ck {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m6x2_mul_ck>;
ti,bit-shift = <0x1f>;
reg = <0x0d00>;
ti,set-bit-to-disable;
};
uart4_fck: uart4_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&per_48m_fck>;
reg = <0x1000>;
ti,bit-shift = <18>;
};
};
&cm_clockdomains {
dpll4_clkdm: dpll4_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll4_ck>;
};
per_clkdm: per_clkdm {
compatible = "ti,clockdomain";
clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
<&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
<&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
<&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
<&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
<&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
<&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
<&mcbsp4_ick>, <&uart4_fck>;
};
};

198
arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi 100644
View File

@ -0,0 +1,198 @@
/*
* Device Tree Source for OMAP34xx/OMAP36xx clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&cm_clocks {
ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&corex2_fck>;
ti,bit-shift = <0>;
reg = <0x0a00>;
};
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&corex2_fck>;
ti,bit-shift = <8>;
reg = <0x0a40>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};
ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
};
ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&ssi_ssr_fck_3430es2>;
clock-mult = <1>;
clock-div = <2>;
};
hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 {
#clock-cells = <0>;
compatible = "ti,omap3-hsotgusb-interface-clock";
clocks = <&core_l3_ick>;
reg = <0x0a10>;
ti,bit-shift = <4>;
};
ssi_l4_ick: ssi_l4_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l4_ick>;
clock-mult = <1>;
clock-div = <1>;
};
ssi_ick_3430es2: ssi_ick_3430es2 {
#clock-cells = <0>;
compatible = "ti,omap3-ssi-interface-clock";
clocks = <&ssi_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <0>;
};
usim_gate_fck: usim_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&omap_96m_fck>;
ti,bit-shift = <9>;
reg = <0x0c00>;
};
sys_d2_ck: sys_d2_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_ck>;
clock-mult = <1>;
clock-div = <2>;
};
omap_96m_d2_fck: omap_96m_d2_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&omap_96m_fck>;
clock-mult = <1>;
clock-div = <2>;
};
omap_96m_d4_fck: omap_96m_d4_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&omap_96m_fck>;
clock-mult = <1>;
clock-div = <4>;
};
omap_96m_d8_fck: omap_96m_d8_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&omap_96m_fck>;
clock-mult = <1>;
clock-div = <8>;
};
omap_96m_d10_fck: omap_96m_d10_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&omap_96m_fck>;
clock-mult = <1>;
clock-div = <10>;
};
dpll5_m2_d4_ck: dpll5_m2_d4_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll5_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
dpll5_m2_d8_ck: dpll5_m2_d8_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll5_m2_ck>;
clock-mult = <1>;
clock-div = <8>;
};
dpll5_m2_d16_ck: dpll5_m2_d16_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll5_m2_ck>;
clock-mult = <1>;
clock-div = <16>;
};
dpll5_m2_d20_ck: dpll5_m2_d20_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll5_m2_ck>;
clock-mult = <1>;
clock-div = <20>;
};
usim_mux_fck: usim_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
ti,bit-shift = <3>;
reg = <0x0c40>;
ti,index-starts-at-one;
};
usim_fck: usim_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&usim_gate_fck>, <&usim_mux_fck>;
};
usim_ick: usim_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&wkup_l4_ick>;
reg = <0x0c10>;
ti,bit-shift = <9>;
};
};
&cm_clockdomains {
core_l3_clkdm: core_l3_clkdm {
compatible = "ti,clockdomain";
clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
};
wkup_clkdm: wkup_clkdm {
compatible = "ti,clockdomain";
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
<&gpt1_ick>, <&usim_ick>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
<&ssi_ick_3430es2>;
};
};

5
arch/arm/boot/dts/omap36xx.dtsi
View File

@ -40,3 +40,8 @@
};
};
};
/include/ "omap36xx-clocks.dtsi"
/include/ "omap34xx-omap36xx-clocks.dtsi"
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

1660
arch/arm/boot/dts/omap3xxx-clocks.dtsi 100644
View File

File diff suppressed because it is too large Load Diff