ARM: at91: pm: Use struct at91_pm_data in pm_suspend.S
The number of register we can safely pass to at91_pm_suspend_in_sram is limited. Instead, pass the address to the at91_pm_data structure. The offsets are automatically generated to avoid hardcoding them. Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>hifive-unleashed-5.1
Alexandre Belloni
parent
9e07c3ce2c
commit
65cc1a59d1
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@ -18,3 +18,36 @@ endif
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ifeq ($(CONFIG_PM_DEBUG),y)
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CFLAGS_pm.o += -DDEBUG
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endif
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# Default sed regexp - multiline due to syntax constraints
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define sed-y
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"/^->/{s:->#\(.*\):/* \1 */:; \
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s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
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s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
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s:->::; p;}"
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endef
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# Use filechk to avoid rebuilds when a header changes, but the resulting file
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# does not
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define filechk_offsets
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(set -e; \
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echo "#ifndef $2"; \
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echo "#define $2"; \
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echo "/*"; \
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echo " * DO NOT MODIFY."; \
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echo " *"; \
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echo " * This file was generated by Kbuild"; \
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echo " */"; \
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echo ""; \
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sed -ne $(sed-y); \
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echo ""; \
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echo "#endif" )
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endef
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arch/arm/mach-at91/pm_data-offsets.s: arch/arm/mach-at91/pm_data-offsets.c
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$(call if_changed_dep,cc_s_c)
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include/generated/at91_pm_data-offsets.h: arch/arm/mach-at91/pm_data-offsets.s FORCE
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$(call filechk,offsets,__PM_DATA_OFFSETS_H__)
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arch/arm/mach-at91/pm_suspend.o: include/generated/at91_pm_data-offsets.h
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@ -37,18 +37,13 @@ extern void at91_pinctrl_gpio_suspend(void);
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extern void at91_pinctrl_gpio_resume(void);
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#endif
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static struct {
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void __iomem *pmc;
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void __iomem *ramc[2];
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unsigned long uhp_udp_mask;
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int memctrl;
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} at91_pm_data;
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static struct at91_pm_data pm_data;
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#define at91_ramc_read(id, field) \
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__raw_readl(at91_pm_data.ramc[id] + field)
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__raw_readl(pm_data.ramc[id] + field)
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#define at91_ramc_write(id, field, value) \
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__raw_writel(value, at91_pm_data.ramc[id] + field)
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__raw_writel(value, pm_data.ramc[id] + field)
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static int at91_pm_valid_state(suspend_state_t state)
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{
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@ -84,10 +79,10 @@ static int at91_pm_verify_clocks(void)
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unsigned long scsr;
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int i;
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scsr = readl(at91_pm_data.pmc + AT91_PMC_SCSR);
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scsr = readl(pm_data.pmc + AT91_PMC_SCSR);
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/* USB must not be using PLLB */
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if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
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if ((scsr & pm_data.uhp_udp_mask) != 0) {
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pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
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return 0;
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}
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@ -98,7 +93,7 @@ static int at91_pm_verify_clocks(void)
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if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
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continue;
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css = readl(at91_pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
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css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
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if (css != AT91_PMC_CSS_SLOW) {
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pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
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return 0;
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@ -124,25 +119,18 @@ int at91_suspend_entering_slow_clock(void)
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}
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EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
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static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
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void __iomem *ramc1, int memctrl);
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extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
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void __iomem *ramc1, int memctrl);
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static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
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extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
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extern u32 at91_pm_suspend_in_sram_sz;
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static void at91_pm_suspend(suspend_state_t state)
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{
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unsigned int pm_data = at91_pm_data.memctrl;
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pm_data |= (state == PM_SUSPEND_MEM) ?
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AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
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pm_data.mode = (state == PM_SUSPEND_MEM) ? AT91_PM_SLOW_CLOCK : 0;
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flush_cache_all();
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outer_disable();
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at91_suspend_sram_fn(at91_pm_data.pmc, at91_pm_data.ramc[0],
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at91_pm_data.ramc[1], pm_data);
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at91_suspend_sram_fn(&pm_data);
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outer_resume();
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}
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@ -245,7 +233,7 @@ static void at91rm9200_standby(void)
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" mcr p15, 0, %0, c7, c0, 4\n\t"
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" str %5, [%1, %2]"
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:
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: "r" (0), "r" (at91_pm_data.ramc[0]), "r" (AT91_MC_SDRAMC_LPR),
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: "r" (0), "r" (pm_data.ramc[0]), "r" (AT91_MC_SDRAMC_LPR),
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"r" (1), "r" (AT91_MC_SDRAMC_SRR),
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"r" (lpr));
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}
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@ -260,7 +248,7 @@ static void at91_ddr_standby(void)
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u32 lpr0, lpr1 = 0;
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u32 saved_lpr0, saved_lpr1 = 0;
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if (at91_pm_data.ramc[1]) {
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if (pm_data.ramc[1]) {
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saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
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lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
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lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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@ -272,13 +260,13 @@ static void at91_ddr_standby(void)
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/* self-refresh mode now */
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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if (at91_pm_data.ramc[1])
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if (pm_data.ramc[1])
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at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
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cpu_do_idle();
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at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
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if (at91_pm_data.ramc[1])
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if (pm_data.ramc[1])
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
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}
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@ -306,7 +294,7 @@ static void at91sam9_sdram_standby(void)
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u32 lpr0, lpr1 = 0;
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u32 saved_lpr0, saved_lpr1 = 0;
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if (at91_pm_data.ramc[1]) {
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if (pm_data.ramc[1]) {
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saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
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lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
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lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
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@ -318,13 +306,13 @@ static void at91sam9_sdram_standby(void)
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/* self-refresh mode now */
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at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
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if (at91_pm_data.ramc[1])
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if (pm_data.ramc[1])
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at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
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cpu_do_idle();
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at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
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if (at91_pm_data.ramc[1])
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if (pm_data.ramc[1])
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at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
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}
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@ -344,8 +332,8 @@ static __init void at91_dt_ramc(void)
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const void *standby = NULL;
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for_each_matching_node_and_match(np, ramc_ids, &of_id) {
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at91_pm_data.ramc[idx] = of_iomap(np, 0);
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if (!at91_pm_data.ramc[idx])
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pm_data.ramc[idx] = of_iomap(np, 0);
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if (!pm_data.ramc[idx])
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panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
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if (!standby)
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@ -371,12 +359,12 @@ static void at91rm9200_idle(void)
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* Disable the processor clock. The processor will be automatically
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* re-enabled by an interrupt or by a reset.
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*/
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writel(AT91_PMC_PCK, at91_pm_data.pmc + AT91_PMC_SCDR);
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writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
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}
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static void at91sam9_idle(void)
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{
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writel(AT91_PMC_PCK, at91_pm_data.pmc + AT91_PMC_SCDR);
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writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
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cpu_do_idle();
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}
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@ -445,8 +433,8 @@ static void __init at91_pm_init(void (*pm_idle)(void))
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platform_device_register(&at91_cpuidle_device);
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pmc_np = of_find_matching_node(NULL, atmel_pmc_ids);
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at91_pm_data.pmc = of_iomap(pmc_np, 0);
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if (!at91_pm_data.pmc) {
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pm_data.pmc = of_iomap(pmc_np, 0);
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if (!pm_data.pmc) {
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pr_err("AT91: PM not supported, PMC not found\n");
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return;
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}
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@ -471,8 +459,8 @@ void __init at91rm9200_pm_init(void)
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*/
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at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
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at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
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at91_pm_data.memctrl = AT91_MEMCTRL_MC;
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pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
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pm_data.memctrl = AT91_MEMCTRL_MC;
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at91_pm_init(at91rm9200_idle);
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}
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@ -480,31 +468,31 @@ void __init at91rm9200_pm_init(void)
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void __init at91sam9260_pm_init(void)
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{
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at91_dt_ramc();
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at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
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at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
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pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
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pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
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at91_pm_init(at91sam9_idle);
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}
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void __init at91sam9g45_pm_init(void)
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{
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at91_dt_ramc();
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at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
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at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
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pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
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pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
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at91_pm_init(at91sam9_idle);
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}
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void __init at91sam9x5_pm_init(void)
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{
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at91_dt_ramc();
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at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
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at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
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pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
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pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
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at91_pm_init(at91sam9_idle);
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}
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void __init sama5_pm_init(void)
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{
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at91_dt_ramc();
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at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
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at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
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pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
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pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
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at91_pm_init(NULL);
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}
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@ -21,12 +21,16 @@
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#define AT91_MEMCTRL_SDRAMC 1
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#define AT91_MEMCTRL_DDRSDR 2
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#define AT91_PM_MEMTYPE_MASK 0x0f
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#define AT91_PM_MODE_OFFSET 4
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#define AT91_PM_MODE_MASK 0x01
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#define AT91_PM_MODE(x) (((x) & AT91_PM_MODE_MASK) << AT91_PM_MODE_OFFSET)
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#define AT91_PM_SLOW_CLOCK 0x01
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#ifndef __ASSEMBLY__
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struct at91_pm_data {
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void __iomem *pmc;
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void __iomem *ramc[2];
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unsigned long uhp_udp_mask;
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unsigned int memctrl;
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unsigned int mode;
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};
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#endif
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#endif
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@ -0,0 +1,13 @@
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#include <linux/stddef.h>
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#include <linux/kbuild.h>
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#include "pm.h"
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int main(void)
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{
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DEFINE(PM_DATA_PMC, offsetof(struct at91_pm_data, pmc));
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DEFINE(PM_DATA_RAMC0, offsetof(struct at91_pm_data, ramc[0]));
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DEFINE(PM_DATA_RAMC1, offsetof(struct at91_pm_data, ramc[1]));
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DEFINE(PM_DATA_MEMCTRL, offsetof(struct at91_pm_data, memctrl));
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DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode));
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return 0;
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}
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@ -14,6 +14,7 @@
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#include <linux/linkage.h>
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#include <linux/clk/at91_pmc.h>
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#include "pm.h"
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#include "generated/at91_pm_data-offsets.h"
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#define SRAMC_SELF_FRESH_ACTIVE 0x01
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#define SRAMC_SELF_FRESH_EXIT 0x00
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@ -72,13 +73,9 @@ tmp2 .req r5
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.arm
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/*
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* void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *sdramc,
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* void __iomem *ramc1, int memctrl)
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* void at91_suspend_sram_fn(struct at91_pm_data*)
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* @input param:
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* @r0: base address of AT91_PMC
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* @r1: base address of SDRAM Controller (SDRAM, DDRSDR, or AT91_SYS)
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* @r2: base address of second SDRAM Controller or 0 if not present
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* @r3: pm information
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* @r0: base address of struct at91_pm_data
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*/
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/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
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.align 3
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@ -90,16 +87,16 @@ ENTRY(at91_pm_suspend_in_sram)
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mov tmp1, #0
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mcr p15, 0, tmp1, c7, c10, 4
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str r0, .pmc_base
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str r1, .sramc_base
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str r2, .sramc1_base
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and r0, r3, #AT91_PM_MEMTYPE_MASK
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str r0, .memtype
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lsr r0, r3, #AT91_PM_MODE_OFFSET
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and r0, r0, #AT91_PM_MODE_MASK
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str r0, .pm_mode
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ldr tmp1, [r0, #PM_DATA_PMC]
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str tmp1, .pmc_base
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ldr tmp1, [r0, #PM_DATA_RAMC0]
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str tmp1, .sramc_base
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ldr tmp1, [r0, #PM_DATA_RAMC1]
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str tmp1, .sramc1_base
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ldr tmp1, [r0, #PM_DATA_MEMCTRL]
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str tmp1, .memtype
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ldr tmp1, [r0, #PM_DATA_MODE]
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str tmp1, .pm_mode
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/* Active the self-refresh mode */
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mov r0, #SRAMC_SELF_FRESH_ACTIVE
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