ARM: sti: Add STiH415 SOC support
The STiH415 is the next generation of HD, AVC set-top box processors for satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9 1.0 GHz, dual-core CPU. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>hifive-unleashed-5.1
Srinivas Kandagatla
Olof Johansson
parent
317ddd256b
commit
65ebcc1158
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@ -0,0 +1,33 @@
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STi ARM Linux Overview
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==========================
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Introduction
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------------
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The ST Microelectronics Multimedia and Application Processors range of
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CortexA9 System-on-Chip are supported by the 'STi' platform of
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ARM Linux. Currently STiH415, STiH416 SOCs are supported with both
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B2000 and B2020 Reference boards.
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configuration
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-------------
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A generic configuration is provided for both STiH415/416, and can be used as the
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default by
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make stih41x_defconfig
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Layout
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------
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All the files for multiple machine families (STiH415, STiH416, and STiG125)
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are located in the platform code contained in arch/arm/mach-sti
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There is a generic board board-dt.c in the mach folder which support
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Flattened Device Tree, which means, It works with any compatible board with
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Device Trees.
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Document Author
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---------------
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Srinivas Kandagatla <srinivas.kandagatla@st.com>, (c) 2013 ST Microelectronics
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@ -0,0 +1,12 @@
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STiH415 Overview
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================
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Introduction
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------------
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The STiH415 is the next generation of HD, AVC set-top box processors
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for satellite, cable, terrestrial and IP-STB markets.
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Features
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- ARM Cortex-A9 1.0 GHz, dual-core CPU
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- SATA2x2,USB 2.0x3, PCIe, Gbit Ethernet MACx2
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@ -1201,6 +1201,15 @@ M: Dinh Nguyen <dinguyen@altera.com>
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S: Maintained
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F: drivers/clk/socfpga/
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ARM/STI ARCHITECTURE
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M: Srinivas Kandagatla <srinivas.kandagatla@st.com>
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M: Stuart Menefy <stuart.menefy@st.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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L: kernel@stlinux.com
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W: http://www.stlinux.com
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S: Maintained
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F: arch/arm/mach-sti/
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ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
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M: Lennert Buytenhek <kernel@wantstofly.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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@ -989,6 +989,8 @@ source "arch/arm/mach-socfpga/Kconfig"
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source "arch/arm/mach-spear/Kconfig"
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source "arch/arm/mach-sti/Kconfig"
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source "arch/arm/mach-s3c24xx/Kconfig"
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if ARCH_S3C64XX
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@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_W90X900) += w90x900
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machine-$(CONFIG_FOOTBRIDGE) += footbridge
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machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
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machine-$(CONFIG_PLAT_SPEAR) += spear
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machine-$(CONFIG_ARCH_STI) += sti
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machine-$(CONFIG_ARCH_VIRT) += virt
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machine-$(CONFIG_ARCH_ZYNQ) += zynq
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machine-$(CONFIG_ARCH_SUNXI) += sunxi
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@ -0,0 +1,71 @@
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#ifndef _ST_PINCFG_H_
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#define _ST_PINCFG_H_
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/* Alternate functions */
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#define ALT1 1
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#define ALT2 2
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#define ALT3 3
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#define ALT4 4
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#define ALT5 5
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#define ALT6 6
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#define ALT7 7
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/* Output enable */
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#define OE (1 << 27)
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/* Pull Up */
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#define PU (1 << 26)
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/* Open Drain */
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#define OD (1 << 26)
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#define RT (1 << 23)
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#define INVERTCLK (1 << 22)
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#define CLKNOTDATA (1 << 21)
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#define DOUBLE_EDGE (1 << 20)
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#define CLK_A (0 << 18)
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#define CLK_B (1 << 18)
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#define CLK_C (2 << 18)
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#define CLK_D (3 << 18)
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/* User-frendly defines for Pin Direction */
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/* oe = 0, pu = 0, od = 0 */
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#define IN (0)
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/* oe = 0, pu = 1, od = 0 */
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#define IN_PU (PU)
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/* oe = 1, pu = 0, od = 0 */
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#define OUT (OE)
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/* oe = 1, pu = 0, od = 1 */
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#define BIDIR (OE | OD)
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/* oe = 1, pu = 1, od = 1 */
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#define BIDIR_PU (OE | PU | OD)
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/* RETIME_TYPE */
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/*
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* B Mode
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* Bypass retime with optional delay parameter
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*/
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#define BYPASS (0)
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/*
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* R0, R1, R0D, R1D modes
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* single-edge data non inverted clock, retime data with clk
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*/
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#define SE_NICLK_IO (RT)
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/*
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* RIV0, RIV1, RIV0D, RIV1D modes
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* single-edge data inverted clock, retime data with clk
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*/
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#define SE_ICLK_IO (RT | INVERTCLK)
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/*
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* R0E, R1E, R0ED, R1ED modes
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* double-edge data, retime data with clk
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*/
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#define DE_IO (RT | DOUBLE_EDGE)
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/*
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* CIV0, CIV1 modes with inverted clock
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* Retiming the clk pins will park clock & reduce the noise within the core.
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*/
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#define ICLK (RT | CLKNOTDATA | INVERTCLK)
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/*
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* CLK0, CLK1 modes with non-inverted clock
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* Retiming the clk pins will park clock & reduce the noise within the core.
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*/
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#define NICLK (RT | CLKNOTDATA)
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#endif /* _ST_PINCFG_H_ */
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@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2013 STMicroelectronics (R&D) Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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clocks {
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/*
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* Fixed 30MHz oscillator input to SoC
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*/
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CLK_SYSIN: CLK_SYSIN {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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};
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: arm_periph_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <500000000>;
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};
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/*
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* Bootloader initialized system infrastructure clock for
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* serial devices.
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*/
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CLKS_ICN_REG_0: CLKS_ICN_REG_0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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};
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};
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};
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@ -0,0 +1,268 @@
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/*
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* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
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* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include "st-pincfg.h"
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/ {
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aliases {
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gpio0 = &PIO0;
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gpio1 = &PIO1;
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gpio2 = &PIO2;
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gpio3 = &PIO3;
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gpio4 = &PIO4;
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gpio5 = &PIO5;
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gpio6 = &PIO6;
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gpio7 = &PIO7;
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gpio8 = &PIO8;
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gpio9 = &PIO9;
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gpio10 = &PIO10;
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gpio11 = &PIO11;
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gpio12 = &PIO12;
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gpio13 = &PIO13;
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gpio14 = &PIO14;
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gpio15 = &PIO15;
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gpio16 = &PIO16;
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gpio17 = &PIO17;
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gpio18 = &PIO18;
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gpio19 = &PIO100;
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gpio20 = &PIO101;
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gpio21 = &PIO102;
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gpio22 = &PIO103;
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gpio23 = &PIO104;
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gpio24 = &PIO105;
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gpio25 = &PIO106;
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gpio26 = &PIO107;
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};
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soc {
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pin-controller-sbc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stih415-sbc-pinctrl";
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st,syscfg = <&syscfg_sbc>;
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ranges = <0 0xfe610000 0x5000>;
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PIO0: gpio@fe610000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0 0x100>;
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st,bank-name = "PIO0";
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};
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PIO1: gpio@fe611000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x1000 0x100>;
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st,bank-name = "PIO1";
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};
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PIO2: gpio@fe612000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x2000 0x100>;
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st,bank-name = "PIO2";
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};
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PIO3: gpio@fe613000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x3000 0x100>;
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st,bank-name = "PIO3";
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};
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PIO4: gpio@fe614000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x4000 0x100>;
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st,bank-name = "PIO4";
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};
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sbc_serial1 {
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pinctrl_sbc_serial1:sbc_serial1 {
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st,pins {
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tx = <&PIO2 6 ALT3 OUT>;
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rx = <&PIO2 7 ALT3 IN>;
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};
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};
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};
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};
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pin-controller-front {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stih415-front-pinctrl";
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st,syscfg = <&syscfg_front>;
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ranges = <0 0xfee00000 0x8000>;
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PIO5: gpio@fee00000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0 0x100>;
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st,bank-name = "PIO5";
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};
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PIO6: gpio@fee01000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x1000 0x100>;
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st,bank-name = "PIO6";
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};
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PIO7: gpio@fee02000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x2000 0x100>;
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st,bank-name = "PIO7";
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};
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PIO8: gpio@fee03000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x3000 0x100>;
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st,bank-name = "PIO8";
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};
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PIO9: gpio@fee04000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x4000 0x100>;
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st,bank-name = "PIO9";
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};
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PIO10: gpio@fee05000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x5000 0x100>;
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st,bank-name = "PIO10";
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};
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PIO11: gpio@fee06000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x6000 0x100>;
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st,bank-name = "PIO11";
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};
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PIO12: gpio@fee07000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x7000 0x100>;
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st,bank-name = "PIO12";
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};
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};
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pin-controller-rear {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stih415-rear-pinctrl";
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st,syscfg = <&syscfg_rear>;
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ranges = <0 0xfe820000 0x8000>;
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PIO13: gpio@fe820000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0 0x100>;
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st,bank-name = "PIO13";
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};
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PIO14: gpio@fe821000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x1000 0x100>;
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st,bank-name = "PIO14";
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};
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PIO15: gpio@fe822000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x2000 0x100>;
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st,bank-name = "PIO15";
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};
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PIO16: gpio@fe823000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x3000 0x100>;
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st,bank-name = "PIO16";
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};
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PIO17: gpio@fe824000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x4000 0x100>;
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st,bank-name = "PIO17";
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};
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PIO18: gpio@fe825000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x5000 0x100>;
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st,bank-name = "PIO18";
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};
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serial2 {
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pinctrl_serial2: serial2-0 {
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st,pins {
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tx = <&PIO17 4 ALT2 OUT>;
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rx = <&PIO17 5 ALT2 IN>;
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};
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};
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};
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};
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pin-controller-left {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stih415-left-pinctrl";
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st,syscfg = <&syscfg_left>;
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ranges = <0 0xfd6b0000 0x3000>;
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PIO100: gpio@fd6b0000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0 0x100>;
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st,bank-name = "PIO100";
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};
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PIO101: gpio@fd6b1000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x1000 0x100>;
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st,bank-name = "PIO101";
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};
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PIO102: gpio@fd6b2000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x2000 0x100>;
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st,bank-name = "PIO102";
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};
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};
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pin-controller-right {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stih415-right-pinctrl";
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st,syscfg = <&syscfg_right>;
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ranges = <0 0xfd330000 0x5000>;
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PIO103: gpio@fd330000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0 0x100>;
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st,bank-name = "PIO103";
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};
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PIO104: gpio@fd331000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x1000 0x100>;
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st,bank-name = "PIO104";
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};
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PIO105: gpio@fd332000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x2000 0x100>;
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st,bank-name = "PIO105";
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};
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PIO106: gpio@fd333000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x3000 0x100>;
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st,bank-name = "PIO106";
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};
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PIO107: gpio@fd334000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0x4000 0x100>;
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st,bank-name = "PIO107";
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};
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};
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};
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};
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@ -0,0 +1,87 @@
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/*
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* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
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* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
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* publishhed by the Free Software Foundation.
|
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*/
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#include "stih41x.dtsi"
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#include "stih415-clock.dtsi"
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#include "stih415-pinctrl.dtsi"
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/ {
|
||||
|
||||
L2: cache-controller {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xfffe2000 0x1000>;
|
||||
arm,data-latency = <3 2 2>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
compatible = "simple-bus";
|
||||
|
||||
syscfg_sbc: sbc-syscfg@fe600000{
|
||||
compatible = "st,stih415-sbc-syscfg", "syscon";
|
||||
reg = <0xfe600000 0xb4>;
|
||||
};
|
||||
|
||||
syscfg_front: front-syscfg@fee10000{
|
||||
compatible = "st,stih415-front-syscfg", "syscon";
|
||||
reg = <0xfee10000 0x194>;
|
||||
};
|
||||
|
||||
syscfg_rear: rear-syscfg@fe830000{
|
||||
compatible = "st,stih415-rear-syscfg", "syscon";
|
||||
reg = <0xfe830000 0x190>;
|
||||
};
|
||||
|
||||
/* MPE syscfgs */
|
||||
syscfg_left: left-syscfg@fd690000{
|
||||
compatible = "st,stih415-left-syscfg", "syscon";
|
||||
reg = <0xfd690000 0x78>;
|
||||
};
|
||||
|
||||
syscfg_right: right-syscfg@fd320000{
|
||||
compatible = "st,stih415-right-syscfg", "syscon";
|
||||
reg = <0xfd320000 0x180>;
|
||||
};
|
||||
|
||||
syscfg_system: system-syscfg@fdde0000 {
|
||||
compatible = "st,stih415-system-syscfg", "syscon";
|
||||
reg = <0xfdde0000 0x15c>;
|
||||
};
|
||||
|
||||
syscfg_lpm: lpm-syscfg@fe4b5100{
|
||||
compatible = "st,stih415-lpm-syscfg", "syscon";
|
||||
reg = <0xfe4b5100 0x08>;
|
||||
};
|
||||
|
||||
serial2: serial@fed32000 {
|
||||
compatible = "st,asc";
|
||||
status = "disabled";
|
||||
reg = <0xfed32000 0x2c>;
|
||||
interrupts = <0 197 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_serial2>;
|
||||
clocks = <&CLKS_ICN_REG_0>;
|
||||
};
|
||||
|
||||
/* SBC comms block ASCs in SASG1 */
|
||||
sbc_serial1: serial@fe531000 {
|
||||
compatible = "st,asc";
|
||||
status = "disabled";
|
||||
reg = <0xfe531000 0x2c>;
|
||||
interrupts = <0 210 0>;
|
||||
clocks = <&CLK_SYSIN>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sbc_serial1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
intc: interrupt-controller@fffe1000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0xfffe1000 0x1000>,
|
||||
<0xfffe0100 0x100>;
|
||||
};
|
||||
|
||||
scu@fffe0000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0xfffe0000 0x1000>;
|
||||
};
|
||||
|
||||
timer@fffe0200 {
|
||||
interrupt-parent = <&intc>;
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0xfffe0200 0x100>;
|
||||
interrupts = <1 11 0x04>;
|
||||
clocks = <&arm_periph_clk>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
menuconfig ARCH_STI
|
||||
bool "STMicroelectronics Consumer Electronics SOCs with Device Trees" if ARCH_MULTI_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select CLKDEV_LOOKUP
|
||||
select ARM_GIC
|
||||
select ARM_GLOBAL_TIMER
|
||||
select PINCTRL
|
||||
select PINCTRL_ST
|
||||
select MFD_SYSCON
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
select HAVE_SMP
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_ERRATA_720789
|
||||
select ARM_ERRATA_754322
|
||||
select PL310_ERRATA_753970 if CACHE_PL310
|
||||
select PL310_ERRATA_769419 if CACHE_PL310
|
||||
help
|
||||
Include support for STiH41x SOCs like STiH415/416 using the device tree
|
||||
for discovery
|
||||
More information at Documentation/arm/STiH41x and
|
||||
at Documentation/devicetree
|
||||
|
||||
|
||||
if ARCH_STI
|
||||
|
||||
config SOC_STIH415
|
||||
bool "STiH415 STMicroelectronics Consumer Electronics family"
|
||||
default y
|
||||
help
|
||||
This enables support for STMicroelectronics Digital Consumer
|
||||
Electronics family StiH415 parts, primarily targetted at set-top-box
|
||||
and other digital audio/video applications using Flattned Device
|
||||
Trees.
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
obj-$(CONFIG_ARCH_STI) += board-dt.o
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
|
||||
* Author(s): Srinivas Kandagatla <srinivas.kandagatla@st.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include "smp.h"
|
||||
|
||||
void __init stih41x_l2x0_init(void)
|
||||
{
|
||||
u32 way_size = 0x4;
|
||||
u32 aux_ctrl;
|
||||
/* may be this can be encoded in macros like BIT*() */
|
||||
aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
|
||||
(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
|
||||
(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
|
||||
(way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
|
||||
|
||||
l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
|
||||
}
|
||||
|
||||
static void __init stih41x_timer_init(void)
|
||||
{
|
||||
of_clk_init(NULL);
|
||||
clocksource_of_init();
|
||||
stih41x_l2x0_init();
|
||||
}
|
||||
|
||||
static const char *stih41x_dt_match[] __initdata = {
|
||||
"st,stih415",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(STM, "STiH415 SoC with Flattened Device Tree")
|
||||
.init_time = stih41x_timer_init,
|
||||
.smp = smp_ops(sti_smp_ops),
|
||||
.dt_compat = stih41x_dt_match,
|
||||
MACHINE_END
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* arch/arm/mach-sti/headsmp.S
|
||||
*
|
||||
* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
|
||||
* http://www.st.com
|
||||
*
|
||||
* Cloned from linux/arch/arm/mach-vexpress/headsmp.S
|
||||
*
|
||||
* Copyright (c) 2003 ARM Limited
|
||||
* All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
__INIT
|
||||
|
||||
/*
|
||||
* ST specific entry point for secondary CPUs. This provides
|
||||
* a "holding pen" into which all secondary cores are held until we're
|
||||
* ready for them to initialise.
|
||||
*/
|
||||
ENTRY(sti_secondary_startup)
|
||||
mrc p15, 0, r0, c0, c0, 5
|
||||
and r0, r0, #15
|
||||
adr r4, 1f
|
||||
ldmia r4, {r5, r6}
|
||||
sub r4, r4, r5
|
||||
add r6, r6, r4
|
||||
pen: ldr r7, [r6]
|
||||
cmp r7, r0
|
||||
bne pen
|
||||
|
||||
/*
|
||||
* we've been released from the holding pen: secondary_stack
|
||||
* should now contain the SVC stack for this core
|
||||
*/
|
||||
b secondary_startup
|
||||
|
||||
1: .long .
|
||||
.long pen_release
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* arch/arm/mach-sti/platsmp.c
|
||||
*
|
||||
* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
|
||||
* http://www.st.com
|
||||
*
|
||||
* Cloned from linux/arch/arm/mach-vexpress/platsmp.c
|
||||
*
|
||||
* Copyright (C) 2002 ARM Ltd.
|
||||
* All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
|
||||
#include "smp.h"
|
||||
|
||||
static void __cpuinit write_pen_release(int val)
|
||||
{
|
||||
pen_release = val;
|
||||
smp_wmb();
|
||||
__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
|
||||
outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(boot_lock);
|
||||
|
||||
void __cpuinit sti_secondary_init(unsigned int cpu)
|
||||
{
|
||||
trace_hardirqs_off();
|
||||
|
||||
/*
|
||||
* let the primary processor know we're out of the
|
||||
* pen, then head off into the C entry point
|
||||
*/
|
||||
write_pen_release(-1);
|
||||
|
||||
/*
|
||||
* Synchronise with the boot thread.
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
spin_unlock(&boot_lock);
|
||||
}
|
||||
|
||||
int __cpuinit sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
unsigned long timeout;
|
||||
|
||||
/*
|
||||
* set synchronisation state between this boot processor
|
||||
* and the secondary one
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
|
||||
/*
|
||||
* The secondary processor is waiting to be released from
|
||||
* the holding pen - release it, then wait for it to flag
|
||||
* that it has been released by resetting pen_release.
|
||||
*
|
||||
* Note that "pen_release" is the hardware CPU ID, whereas
|
||||
* "cpu" is Linux's internal ID.
|
||||
*/
|
||||
write_pen_release(cpu_logical_map(cpu));
|
||||
|
||||
/*
|
||||
* Send the secondary CPU a soft interrupt, thereby causing
|
||||
* it to jump to the secondary entrypoint.
|
||||
*/
|
||||
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
|
||||
|
||||
timeout = jiffies + (1 * HZ);
|
||||
while (time_before(jiffies, timeout)) {
|
||||
smp_rmb();
|
||||
if (pen_release == -1)
|
||||
break;
|
||||
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
/*
|
||||
* now the secondary core is starting up let it run its
|
||||
* calibrations, then wait for it to finish
|
||||
*/
|
||||
spin_unlock(&boot_lock);
|
||||
|
||||
return pen_release != -1 ? -ENOSYS : 0;
|
||||
}
|
||||
|
||||
void __init sti_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
void __iomem *scu_base = NULL;
|
||||
struct device_node *np = of_find_compatible_node(
|
||||
NULL, NULL, "arm,cortex-a9-scu");
|
||||
if (np) {
|
||||
scu_base = of_iomap(np, 0);
|
||||
scu_enable(scu_base);
|
||||
of_node_put(np);
|
||||
}
|
||||
}
|
||||
|
||||
struct smp_operations __initdata sti_smp_ops = {
|
||||
.smp_prepare_cpus = sti_smp_prepare_cpus,
|
||||
.smp_secondary_init = sti_secondary_init,
|
||||
.smp_boot_secondary = sti_boot_secondary,
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* arch/arm/mach-sti/smp.h
|
||||
*
|
||||
* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
|
||||
* http://www.st.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_STI_SMP_H
|
||||
#define __MACH_STI_SMP_H
|
||||
|
||||
extern struct smp_operations sti_smp_ops;
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue