firmware: qcom_scm: Order functions, definitions by service/command
Definitions throughout qcom_scm are loosely grouped and loosely ordered. Sort all the functions/definitions by service ID/command ID to improve sanity when needing to add new functionality to this driver. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-16-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>alistair/sensors
Elliot Berman
Bjorn Andersson
parent
59b6cf3046
commit
65f0c90b7d
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@ -84,6 +84,20 @@ static void qcom_scm_clk_disable(void)
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clk_disable_unprepare(__scm->bus_clk);
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}
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/**
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* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
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* @entry: Entry point function for the cpus
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* @cpus: The cpumask of cpus that will use the entry point
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*
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* Set the Linux entry point for the SCM to transfer control to when coming
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* out of a power down. CPU power down may be executed on cpuidle or hotplug.
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*/
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int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
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{
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return __qcom_scm_set_warm_boot_addr(__scm->dev, entry, cpus);
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}
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EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
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/**
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* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
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* @entry: Entry point function for the cpus
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@ -99,20 +113,6 @@ int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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}
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EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
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/**
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* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
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* @entry: Entry point function for the cpus
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* @cpus: The cpumask of cpus that will use the entry point
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*
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* Set the Linux entry point for the SCM to transfer control to when coming
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* out of a power down. CPU power down may be executed on cpuidle or hotplug.
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*/
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int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
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{
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return __qcom_scm_set_warm_boot_addr(__scm->dev, entry, cpus);
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}
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EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
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/**
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* qcom_scm_cpu_power_down() - Power down the cpu
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* @flags - Flags to flush cache
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@ -127,107 +127,33 @@ void qcom_scm_cpu_power_down(u32 flags)
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}
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EXPORT_SYMBOL(qcom_scm_cpu_power_down);
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/**
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* qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
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*
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* Return true if HDCP is supported, false if not.
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*/
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bool qcom_scm_hdcp_available(void)
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int qcom_scm_set_remote_state(u32 state, u32 id)
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{
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int ret = qcom_scm_clk_enable();
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return __qcom_scm_set_remote_state(__scm->dev, state, id);
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}
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EXPORT_SYMBOL(qcom_scm_set_remote_state);
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static void qcom_scm_set_download_mode(bool enable)
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{
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bool avail;
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int ret = 0;
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avail = __qcom_scm_is_call_available(__scm->dev,
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QCOM_SCM_SVC_BOOT,
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QCOM_SCM_BOOT_SET_DLOAD_MODE);
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if (avail) {
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ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
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} else if (__scm->dload_mode_addr) {
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ret = __qcom_scm_io_writel(__scm->dev, __scm->dload_mode_addr,
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enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
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} else {
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dev_err(__scm->dev,
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"No available mechanism for setting download mode\n");
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}
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if (ret)
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return ret;
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ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
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QCOM_SCM_HDCP_INVOKE);
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qcom_scm_clk_disable();
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return ret > 0 ? true : false;
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dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
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}
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EXPORT_SYMBOL(qcom_scm_hdcp_available);
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/**
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* qcom_scm_hdcp_req() - Send HDCP request.
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* @req: HDCP request array
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* @req_cnt: HDCP request array count
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* @resp: response buffer passed to SCM
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*
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* Write HDCP register(s) through SCM.
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*/
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int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
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{
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int ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = __qcom_scm_hdcp_req(__scm->dev, req, req_cnt, resp);
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qcom_scm_clk_disable();
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return ret;
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}
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EXPORT_SYMBOL(qcom_scm_hdcp_req);
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/**
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* qcom_scm_pas_supported() - Check if the peripheral authentication service is
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* available for the given peripherial
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* @peripheral: peripheral id
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*
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* Returns true if PAS is supported for this peripheral, otherwise false.
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*/
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bool qcom_scm_pas_supported(u32 peripheral)
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{
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int ret;
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ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PIL_PAS_IS_SUPPORTED);
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if (ret <= 0)
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return false;
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return __qcom_scm_pas_supported(__scm->dev, peripheral);
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}
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EXPORT_SYMBOL(qcom_scm_pas_supported);
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/**
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* qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
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*/
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bool qcom_scm_ocmem_lock_available(void)
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{
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return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM,
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QCOM_SCM_OCMEM_LOCK_CMD);
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}
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EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
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/**
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* qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
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* region to the specified initiator
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*
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* @id: tz initiator id
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* @offset: OCMEM offset
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* @size: OCMEM size
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* @mode: access mode (WIDE/NARROW)
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*/
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int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size,
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u32 mode)
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{
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return __qcom_scm_ocmem_lock(__scm->dev, id, offset, size, mode);
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}
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EXPORT_SYMBOL(qcom_scm_ocmem_lock);
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/**
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* qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM
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* region from the specified initiator
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*
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* @id: tz initiator id
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* @offset: OCMEM offset
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* @size: OCMEM size
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*/
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int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size)
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{
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return __qcom_scm_ocmem_unlock(__scm->dev, id, offset, size);
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}
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EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
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/**
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* qcom_scm_pas_init_image() - Initialize peripheral authentication service
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@ -342,6 +268,26 @@ int qcom_scm_pas_shutdown(u32 peripheral)
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}
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EXPORT_SYMBOL(qcom_scm_pas_shutdown);
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/**
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* qcom_scm_pas_supported() - Check if the peripheral authentication service is
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* available for the given peripherial
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* @peripheral: peripheral id
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*
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* Returns true if PAS is supported for this peripheral, otherwise false.
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*/
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bool qcom_scm_pas_supported(u32 peripheral)
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{
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int ret;
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ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
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QCOM_SCM_PIL_PAS_IS_SUPPORTED);
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if (ret <= 0)
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return false;
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return __qcom_scm_pas_supported(__scm->dev, peripheral);
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}
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EXPORT_SYMBOL(qcom_scm_pas_supported);
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static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long idx)
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{
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@ -365,6 +311,18 @@ static const struct reset_control_ops qcom_scm_pas_reset_ops = {
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.deassert = qcom_scm_pas_reset_deassert,
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};
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int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
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{
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return __qcom_scm_io_readl(__scm->dev, addr, val);
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}
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EXPORT_SYMBOL(qcom_scm_io_readl);
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int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
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{
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return __qcom_scm_io_writel(__scm->dev, addr, val);
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}
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EXPORT_SYMBOL(qcom_scm_io_writel);
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/**
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* qcom_scm_restore_sec_cfg_available() - Check if secure environment
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* supports restore security config interface.
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@ -396,87 +354,6 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
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}
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EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
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int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
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{
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return __qcom_scm_qsmmu500_wait_safe_toggle(__scm->dev, en);
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}
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EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
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int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
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{
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return __qcom_scm_io_readl(__scm->dev, addr, val);
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}
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EXPORT_SYMBOL(qcom_scm_io_readl);
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int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
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{
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return __qcom_scm_io_writel(__scm->dev, addr, val);
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}
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EXPORT_SYMBOL(qcom_scm_io_writel);
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static void qcom_scm_set_download_mode(bool enable)
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{
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bool avail;
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int ret = 0;
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avail = __qcom_scm_is_call_available(__scm->dev,
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QCOM_SCM_SVC_BOOT,
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QCOM_SCM_BOOT_SET_DLOAD_MODE);
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if (avail) {
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ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
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} else if (__scm->dload_mode_addr) {
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ret = __qcom_scm_io_writel(__scm->dev, __scm->dload_mode_addr,
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enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
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} else {
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dev_err(__scm->dev,
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"No available mechanism for setting download mode\n");
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}
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if (ret)
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dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
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}
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static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
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{
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struct device_node *tcsr;
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struct device_node *np = dev->of_node;
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struct resource res;
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u32 offset;
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int ret;
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tcsr = of_parse_phandle(np, "qcom,dload-mode", 0);
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if (!tcsr)
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return 0;
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ret = of_address_to_resource(tcsr, 0, &res);
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of_node_put(tcsr);
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if (ret)
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return ret;
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ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset);
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if (ret < 0)
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return ret;
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*addr = res.start + offset;
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return 0;
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}
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/**
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* qcom_scm_is_available() - Checks if SCM is available
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*/
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bool qcom_scm_is_available(void)
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{
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return !!__scm;
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}
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EXPORT_SYMBOL(qcom_scm_is_available);
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int qcom_scm_set_remote_state(u32 state, u32 id)
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{
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return __qcom_scm_set_remote_state(__scm->dev, state, id);
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}
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EXPORT_SYMBOL(qcom_scm_set_remote_state);
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/**
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* qcom_scm_assign_mem() - Make a secure call to reassign memory ownership
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* @mem_addr: mem region whose ownership need to be reassigned
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@ -559,6 +436,129 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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}
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EXPORT_SYMBOL(qcom_scm_assign_mem);
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/**
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* qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
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*/
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bool qcom_scm_ocmem_lock_available(void)
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{
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return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM,
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QCOM_SCM_OCMEM_LOCK_CMD);
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}
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EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
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/**
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* qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
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* region to the specified initiator
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*
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* @id: tz initiator id
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* @offset: OCMEM offset
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* @size: OCMEM size
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* @mode: access mode (WIDE/NARROW)
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*/
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int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size,
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u32 mode)
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{
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return __qcom_scm_ocmem_lock(__scm->dev, id, offset, size, mode);
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}
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EXPORT_SYMBOL(qcom_scm_ocmem_lock);
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/**
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* qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM
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* region from the specified initiator
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*
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* @id: tz initiator id
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* @offset: OCMEM offset
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* @size: OCMEM size
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*/
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int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size)
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{
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return __qcom_scm_ocmem_unlock(__scm->dev, id, offset, size);
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}
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EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
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/**
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* qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
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*
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* Return true if HDCP is supported, false if not.
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*/
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bool qcom_scm_hdcp_available(void)
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{
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int ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
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QCOM_SCM_HDCP_INVOKE);
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qcom_scm_clk_disable();
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return ret > 0 ? true : false;
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}
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EXPORT_SYMBOL(qcom_scm_hdcp_available);
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/**
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* qcom_scm_hdcp_req() - Send HDCP request.
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* @req: HDCP request array
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* @req_cnt: HDCP request array count
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* @resp: response buffer passed to SCM
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*
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* Write HDCP register(s) through SCM.
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*/
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int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
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{
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int ret = qcom_scm_clk_enable();
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if (ret)
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return ret;
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ret = __qcom_scm_hdcp_req(__scm->dev, req, req_cnt, resp);
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qcom_scm_clk_disable();
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return ret;
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}
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EXPORT_SYMBOL(qcom_scm_hdcp_req);
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int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
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{
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return __qcom_scm_qsmmu500_wait_safe_toggle(__scm->dev, en);
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}
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EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
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static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
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{
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struct device_node *tcsr;
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struct device_node *np = dev->of_node;
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struct resource res;
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u32 offset;
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int ret;
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tcsr = of_parse_phandle(np, "qcom,dload-mode", 0);
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if (!tcsr)
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return 0;
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ret = of_address_to_resource(tcsr, 0, &res);
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of_node_put(tcsr);
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if (ret)
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return ret;
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ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset);
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if (ret < 0)
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return ret;
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*addr = res.start + offset;
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return 0;
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}
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/**
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* qcom_scm_is_available() - Checks if SCM is available
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*/
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bool qcom_scm_is_available(void)
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{
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return !!__scm;
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}
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EXPORT_SYMBOL(qcom_scm_is_available);
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static int qcom_scm_probe(struct platform_device *pdev)
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{
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struct qcom_scm *scm;
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|
|
@ -4,56 +4,27 @@
|
|||
#ifndef __QCOM_SCM_INT_H
|
||||
#define __QCOM_SCM_INT_H
|
||||
|
||||
#define QCOM_SCM_SVC_BOOT 0x1
|
||||
#define QCOM_SCM_BOOT_SET_ADDR 0x1
|
||||
#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
|
||||
#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0xa
|
||||
extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
|
||||
extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
|
||||
|
||||
#define QCOM_SCM_SVC_BOOT 0x01
|
||||
#define QCOM_SCM_BOOT_SET_ADDR 0x01
|
||||
#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
|
||||
#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
|
||||
#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
|
||||
extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
|
||||
const cpumask_t *cpus);
|
||||
extern int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry,
|
||||
const cpumask_t *cpus);
|
||||
|
||||
#define QCOM_SCM_BOOT_TERMINATE_PC 0x2
|
||||
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
|
||||
extern void __qcom_scm_cpu_power_down(struct device *dev, u32 flags);
|
||||
extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
|
||||
extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
|
||||
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
|
||||
|
||||
#define QCOM_SCM_SVC_IO 0x5
|
||||
#define QCOM_SCM_IO_READ 0x1
|
||||
#define QCOM_SCM_IO_WRITE 0x2
|
||||
extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);
|
||||
extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);
|
||||
|
||||
#define QCOM_SCM_SVC_INFO 0x6
|
||||
#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x1
|
||||
extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
|
||||
u32 cmd_id);
|
||||
|
||||
#define QCOM_SCM_SVC_HDCP 0x11
|
||||
#define QCOM_SCM_HDCP_INVOKE 0x01
|
||||
extern int __qcom_scm_hdcp_req(struct device *dev,
|
||||
struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
|
||||
|
||||
extern void __qcom_scm_init(void);
|
||||
|
||||
#define QCOM_SCM_SVC_OCMEM 0xf
|
||||
#define QCOM_SCM_OCMEM_LOCK_CMD 0x1
|
||||
#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x2
|
||||
|
||||
extern int __qcom_scm_ocmem_lock(struct device *dev, u32 id, u32 offset,
|
||||
u32 size, u32 mode);
|
||||
extern int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset,
|
||||
u32 size);
|
||||
|
||||
#define QCOM_SCM_SVC_PIL 0x2
|
||||
#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x1
|
||||
#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x2
|
||||
#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x5
|
||||
#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x6
|
||||
#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x7
|
||||
#define QCOM_SCM_PIL_PAS_MSS_RESET 0xa
|
||||
#define QCOM_SCM_SVC_PIL 0x02
|
||||
#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
|
||||
#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
|
||||
#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
|
||||
#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
|
||||
#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
|
||||
#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
|
||||
extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);
|
||||
extern int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
|
||||
dma_addr_t metadata_phys);
|
||||
|
|
@ -63,6 +34,54 @@ extern int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);
|
|||
extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
|
||||
extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
|
||||
|
||||
#define QCOM_SCM_SVC_IO 0x05
|
||||
#define QCOM_SCM_IO_READ 0x01
|
||||
#define QCOM_SCM_IO_WRITE 0x02
|
||||
extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);
|
||||
extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);
|
||||
|
||||
#define QCOM_SCM_SVC_INFO 0x06
|
||||
#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
|
||||
extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
|
||||
u32 cmd_id);
|
||||
|
||||
#define QCOM_SCM_SVC_MP 0x0c
|
||||
#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
|
||||
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
|
||||
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
|
||||
#define QCOM_SCM_MP_ASSIGN 0x16
|
||||
extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
|
||||
u32 spare);
|
||||
extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
|
||||
size_t *size);
|
||||
extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
|
||||
u32 size, u32 spare);
|
||||
extern int __qcom_scm_assign_mem(struct device *dev,
|
||||
phys_addr_t mem_region, size_t mem_sz,
|
||||
phys_addr_t src, size_t src_sz,
|
||||
phys_addr_t dest, size_t dest_sz);
|
||||
|
||||
#define QCOM_SCM_SVC_OCMEM 0x0f
|
||||
#define QCOM_SCM_OCMEM_LOCK_CMD 0x01
|
||||
#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02
|
||||
extern int __qcom_scm_ocmem_lock(struct device *dev, u32 id, u32 offset,
|
||||
u32 size, u32 mode);
|
||||
extern int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset,
|
||||
u32 size);
|
||||
|
||||
#define QCOM_SCM_SVC_HDCP 0x11
|
||||
#define QCOM_SCM_HDCP_INVOKE 0x01
|
||||
extern int __qcom_scm_hdcp_req(struct device *dev,
|
||||
struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
|
||||
|
||||
#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
|
||||
#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
|
||||
#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
|
||||
extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev,
|
||||
bool enable);
|
||||
|
||||
extern void __qcom_scm_init(void);
|
||||
|
||||
/* common error codes */
|
||||
#define QCOM_SCM_V2_EBUSY -12
|
||||
#define QCOM_SCM_ENOMEM -5
|
||||
|
|
@ -90,25 +109,4 @@ static inline int qcom_scm_remap_error(int err)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
#define QCOM_SCM_SVC_MP 0xc
|
||||
#define QCOM_SCM_MP_RESTORE_SEC_CFG 2
|
||||
extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
|
||||
u32 spare);
|
||||
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 3
|
||||
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 4
|
||||
#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
|
||||
#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x3
|
||||
#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x2
|
||||
extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
|
||||
size_t *size);
|
||||
extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
|
||||
u32 size, u32 spare);
|
||||
extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev,
|
||||
bool enable);
|
||||
#define QCOM_SCM_MP_ASSIGN 0x16
|
||||
extern int __qcom_scm_assign_mem(struct device *dev,
|
||||
phys_addr_t mem_region, size_t mem_sz,
|
||||
phys_addr_t src, size_t src_sz,
|
||||
phys_addr_t dest, size_t dest_sz);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
|
||||
/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
|
||||
* Copyright (C) 2015 Linaro Ltd.
|
||||
*/
|
||||
#ifndef __QCOM_SCM_H
|
||||
|
|
@ -55,81 +55,94 @@ enum qcom_scm_sec_dev_id {
|
|||
#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_SCM)
|
||||
extern bool qcom_scm_is_available(void);
|
||||
|
||||
extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
|
||||
extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
|
||||
extern bool qcom_scm_is_available(void);
|
||||
extern bool qcom_scm_hdcp_available(void);
|
||||
extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
|
||||
u32 *resp);
|
||||
extern bool qcom_scm_ocmem_lock_available(void);
|
||||
extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
|
||||
u32 size, u32 mode);
|
||||
extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
|
||||
u32 size);
|
||||
extern bool qcom_scm_pas_supported(u32 peripheral);
|
||||
extern void qcom_scm_cpu_power_down(u32 flags);
|
||||
extern int qcom_scm_set_remote_state(u32 state, u32 id);
|
||||
|
||||
extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
|
||||
size_t size);
|
||||
extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
|
||||
phys_addr_t size);
|
||||
extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
|
||||
extern int qcom_scm_pas_shutdown(u32 peripheral);
|
||||
extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
|
||||
unsigned int *src,
|
||||
const struct qcom_scm_vmperm *newvm,
|
||||
unsigned int dest_cnt);
|
||||
extern void qcom_scm_cpu_power_down(u32 flags);
|
||||
extern int qcom_scm_set_remote_state(u32 state, u32 id);
|
||||
extern bool qcom_scm_pas_supported(u32 peripheral);
|
||||
|
||||
extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
|
||||
extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
|
||||
|
||||
extern bool qcom_scm_restore_sec_cfg_available(void);
|
||||
extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
|
||||
extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
|
||||
extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
|
||||
extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
|
||||
unsigned int *src,
|
||||
const struct qcom_scm_vmperm *newvm,
|
||||
unsigned int dest_cnt);
|
||||
|
||||
extern bool qcom_scm_ocmem_lock_available(void);
|
||||
extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
|
||||
u32 size, u32 mode);
|
||||
extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
|
||||
u32 size);
|
||||
|
||||
extern bool qcom_scm_hdcp_available(void);
|
||||
extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
|
||||
u32 *resp);
|
||||
|
||||
extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
|
||||
extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
|
||||
extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
|
||||
#else
|
||||
|
||||
#include <linux/errno.h>
|
||||
|
||||
static inline
|
||||
int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline
|
||||
int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline bool qcom_scm_is_available(void) { return false; }
|
||||
static inline bool qcom_scm_hdcp_available(void) { return false; }
|
||||
static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
|
||||
u32 *resp) { return -ENODEV; }
|
||||
|
||||
static inline int qcom_scm_set_cold_boot_addr(void *entry,
|
||||
const cpumask_t *cpus) { return -ENODEV; }
|
||||
static inline int qcom_scm_set_warm_boot_addr(void *entry,
|
||||
const cpumask_t *cpus) { return -ENODEV; }
|
||||
static inline void qcom_scm_cpu_power_down(u32 flags) {}
|
||||
static inline u32 qcom_scm_set_remote_state(u32 state,u32 id)
|
||||
{ return -ENODEV; }
|
||||
|
||||
static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
|
||||
size_t size) { return -ENODEV; }
|
||||
static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
|
||||
phys_addr_t size) { return -ENODEV; }
|
||||
static inline int qcom_scm_pas_auth_and_reset(u32 peripheral)
|
||||
{ return -ENODEV; }
|
||||
static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
|
||||
static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
|
||||
|
||||
static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
|
||||
{ return -ENODEV; }
|
||||
static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
|
||||
{ return -ENODEV; }
|
||||
|
||||
static inline bool qcom_scm_restore_sec_cfg_available(void) { return false; }
|
||||
static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
|
||||
{ return -ENODEV; }
|
||||
static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
|
||||
{ return -ENODEV; }
|
||||
static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
|
||||
{ return -ENODEV; }
|
||||
static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
|
||||
unsigned int *src, const struct qcom_scm_vmperm *newvm,
|
||||
unsigned int dest_cnt) { return -ENODEV; }
|
||||
|
||||
static inline bool qcom_scm_ocmem_lock_available(void) { return false; }
|
||||
static inline int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
|
||||
u32 size, u32 mode) { return -ENODEV; }
|
||||
static inline int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
|
||||
u32 size) { return -ENODEV; }
|
||||
static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
|
||||
static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
|
||||
size_t size) { return -ENODEV; }
|
||||
static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
|
||||
phys_addr_t size) { return -ENODEV; }
|
||||
static inline int
|
||||
qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
|
||||
static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
|
||||
static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
|
||||
unsigned int *src,
|
||||
const struct qcom_scm_vmperm *newvm,
|
||||
unsigned int dest_cnt) { return -ENODEV; }
|
||||
static inline void qcom_scm_cpu_power_down(u32 flags) {}
|
||||
static inline u32
|
||||
qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
|
||||
static inline bool qcom_scm_restore_sec_cfg_available(void) { return false; }
|
||||
static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
|
||||
static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
|
||||
static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
|
||||
static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { return -ENODEV; }
|
||||
static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
|
||||
static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
|
||||
u32 size, u32 mode) { return -ENODEV; }
|
||||
static inline int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id,
|
||||
u32 offset, u32 size) { return -ENODEV; }
|
||||
|
||||
static inline bool qcom_scm_hdcp_available(void) { return false; }
|
||||
static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
|
||||
u32 *resp) { return -ENODEV; }
|
||||
|
||||
static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
|
||||
{ return -ENODEV; }
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue