ARM: mach-shmobile: bonito: Add LCDC0 support
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Kuninori Morimoto
Paul Mundt
parent
e609b7cb7a
commit
665ccfa090
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@ -33,6 +33,7 @@
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#include <asm/mach/time.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <mach/r8a7740.h>
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#include <video/sh_mobile_lcdc.h>
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/*
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* CS Address device note
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@ -64,6 +65,13 @@
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* S43.1 = ON
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*/
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/*
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* LCDC0 (CN3/CN4/CN7)
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*
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* S38.1 = OFF
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* S38.2 = OFF
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*/
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/*
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* FPGA
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*/
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@ -72,6 +80,7 @@
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#define BUSSWMR3 0x0074
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#define BUSSWMR4 0x0076
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#define LCDCR 0x10B4
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#define A1MDSR 0x10E0
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#define BVERR 0x1100
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static u16 bonito_fpga_read(u32 offset)
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@ -134,6 +143,63 @@ static int __init pmic_init(void)
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}
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device_initcall(pmic_init);
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/*
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* LCDC0
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*/
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static const struct fb_videomode lcdc0_mode = {
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.name = "WVGA Panel",
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.xres = 800,
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.yres = 480,
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.left_margin = 88,
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.right_margin = 40,
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.hsync_len = 128,
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.upper_margin = 20,
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.lower_margin = 5,
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.vsync_len = 5,
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.sync = 0,
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};
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static struct sh_mobile_lcdc_info lcdc0_info = {
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.clock_source = LCDC_CLK_BUS,
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.ch[0] = {
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.chan = LCDC_CHAN_MAINLCD,
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.bpp = 16,
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.interface_type = RGB24,
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.clock_divider = 5,
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.flags = 0,
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.lcd_cfg = &lcdc0_mode,
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.num_cfg = 1,
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.lcd_size_cfg = {
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.width = 152,
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.height = 91,
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},
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},
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};
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static struct resource lcdc0_resources[] = {
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[0] = {
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.name = "LCDC0",
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.start = 0xfe940000,
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.end = 0xfe943fff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = intcs_evt2irq(0x0580),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device lcdc0_device = {
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.name = "sh_mobile_lcdc_fb",
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.id = 0,
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.resource = lcdc0_resources,
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.num_resources = ARRAY_SIZE(lcdc0_resources),
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.dev = {
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.platform_data = &lcdc0_info,
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.coherent_dma_mask = ~0,
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},
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};
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/*
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* core board devices
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*/
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@ -144,6 +210,7 @@ static struct platform_device *bonito_core_devices[] __initdata = {
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* base board devices
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*/
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static struct platform_device *bonito_base_devices[] __initdata = {
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&lcdc0_device,
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};
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/*
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@ -199,6 +266,9 @@ static void __init bonito_map_io(void)
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#define BIT_ON(sw, bit) (sw & (1 << bit))
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#define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
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#define VCCQ1CR 0xE6058140
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#define VCCQ1LCDCR 0xE6058186
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static void __init bonito_init(void)
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{
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u16 val;
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@ -258,6 +328,53 @@ static void __init bonito_init(void)
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gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
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}
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/*
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* LCDC0 (CN3)
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*/
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if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
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BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
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gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
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gpio_request(GPIO_FN_LCD0_D0, NULL);
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gpio_request(GPIO_FN_LCD0_D1, NULL);
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gpio_request(GPIO_FN_LCD0_D2, NULL);
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gpio_request(GPIO_FN_LCD0_D3, NULL);
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gpio_request(GPIO_FN_LCD0_D4, NULL);
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gpio_request(GPIO_FN_LCD0_D5, NULL);
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gpio_request(GPIO_FN_LCD0_D6, NULL);
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gpio_request(GPIO_FN_LCD0_D7, NULL);
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gpio_request(GPIO_FN_LCD0_D8, NULL);
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gpio_request(GPIO_FN_LCD0_D9, NULL);
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gpio_request(GPIO_FN_LCD0_D10, NULL);
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gpio_request(GPIO_FN_LCD0_D11, NULL);
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gpio_request(GPIO_FN_LCD0_D12, NULL);
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gpio_request(GPIO_FN_LCD0_D13, NULL);
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gpio_request(GPIO_FN_LCD0_D14, NULL);
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gpio_request(GPIO_FN_LCD0_D15, NULL);
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gpio_request(GPIO_FN_LCD0_D16, NULL);
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gpio_request(GPIO_FN_LCD0_D17, NULL);
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gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
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gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
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gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
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gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
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gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
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gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
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gpio_request(GPIO_FN_LCD0_DCK, NULL);
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gpio_request(GPIO_FN_LCD0_VSYN, NULL);
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gpio_request(GPIO_FN_LCD0_HSYN, NULL);
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gpio_request(GPIO_FN_LCD0_DISP, NULL);
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gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
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gpio_request(GPIO_PORT61, NULL); /* LCDDON */
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gpio_direction_output(GPIO_PORT61, 1);
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/* backlight on */
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bonito_fpga_write(LCDCR, 1);
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/* drivability Max */
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__raw_writew(0x00FF , VCCQ1LCDCR);
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__raw_writew(0xFFFF , VCCQ1CR);
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}
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platform_add_devices(bonito_base_devices,
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ARRAY_SIZE(bonito_base_devices));
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}
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@ -251,7 +251,7 @@ static struct clk div6_clks[DIV6_NR] = {
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enum {
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MSTP125,
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MSTP116, MSTP111,
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MSTP116, MSTP111, MSTP100, MSTP117,
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MSTP230,
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MSTP222,
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@ -264,8 +264,10 @@ enum {
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
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[MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
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[MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
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[MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
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[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
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[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
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[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
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@ -314,8 +316,10 @@ static struct clk_lookup lookups[] = {
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CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
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/* MSTP32 clocks */
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CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]),
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CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]),
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CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
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CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
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CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
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CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
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