drm/tegra: dc: Unify enabling the display controller
Previously output drivers would enable continuous display mode and power up the display controller at various points during the initialization. This is suboptimal because it accesses display controller registers in output drivers and duplicates a bit of code. Move this code into the display controller driver and enable the display controller as the final step of the ->mode_set_nofb() implementation. Signed-off-by: Thierry Reding <treding@nvidia.com>hifive-unleashed-5.1
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8f604f8c4d
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666cb87332
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@ -1236,6 +1236,18 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
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value &= ~INTERLACE_ENABLE;
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value &= ~INTERLACE_ENABLE;
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tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
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tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
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}
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}
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value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
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value &= ~DISP_CTRL_MODE_MASK;
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value |= DISP_CTRL_MODE_C_DISPLAY;
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tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
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value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
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value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
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PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
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tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
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tegra_dc_commit(dc);
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}
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}
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static void tegra_crtc_prepare(struct drm_crtc *crtc)
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static void tegra_crtc_prepare(struct drm_crtc *crtc)
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@ -824,16 +824,6 @@ static void tegra_dsi_encoder_mode_set(struct drm_encoder *encoder,
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value |= DSI_ENABLE;
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value |= DSI_ENABLE;
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tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
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tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
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value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
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value &= ~DISP_CTRL_MODE_MASK;
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value |= DISP_CTRL_MODE_C_DISPLAY;
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tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
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value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
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value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
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PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
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tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
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tegra_dc_commit(dc);
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tegra_dc_commit(dc);
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/* enable DSI controller */
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/* enable DSI controller */
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@ -1022,16 +1022,6 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder,
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value |= HDMI_ENABLE;
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value |= HDMI_ENABLE;
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tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
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tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
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value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
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value &= ~DISP_CTRL_MODE_MASK;
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value |= DISP_CTRL_MODE_C_DISPLAY;
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tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
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value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
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value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
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PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
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tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
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tegra_dc_commit(dc);
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tegra_dc_commit(dc);
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/* TODO: add HDCP support */
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/* TODO: add HDCP support */
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@ -168,16 +168,6 @@ static void tegra_rgb_encoder_mode_set(struct drm_encoder *encoder,
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value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
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value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
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tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
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tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
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value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_COMMAND);
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value &= ~DISP_CTRL_MODE_MASK;
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value |= DISP_CTRL_MODE_C_DISPLAY;
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tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_COMMAND);
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value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL);
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value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
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PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
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tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
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tegra_dc_commit(rgb->dc);
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tegra_dc_commit(rgb->dc);
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if (output->panel)
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if (output->panel)
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@ -193,6 +183,7 @@ static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
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drm_panel_disable(output->panel);
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drm_panel_disable(output->panel);
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tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
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tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
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tegra_dc_commit(rgb->dc);
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if (output->panel)
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if (output->panel)
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drm_panel_unprepare(output->panel);
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drm_panel_unprepare(output->panel);
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@ -261,17 +261,8 @@ static int tegra_sor_attach(struct tegra_sor *sor)
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static int tegra_sor_wakeup(struct tegra_sor *sor)
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static int tegra_sor_wakeup(struct tegra_sor *sor)
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{
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{
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struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
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unsigned long value, timeout;
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unsigned long value, timeout;
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/* enable display controller outputs */
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value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
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value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
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PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
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tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
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tegra_dc_commit(dc);
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timeout = jiffies + msecs_to_jiffies(250);
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timeout = jiffies + msecs_to_jiffies(250);
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/* wait for head to wake up */
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/* wait for head to wake up */
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@ -1112,18 +1103,6 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
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goto unlock;
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goto unlock;
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}
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}
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/* start display controller in continuous mode */
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value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
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value |= WRITE_MUX;
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tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);
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tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
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tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
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value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
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value &= ~WRITE_MUX;
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tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);
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/*
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/*
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* configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
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* configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
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* raster, associate with display controller)
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* raster, associate with display controller)
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@ -1198,11 +1177,13 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
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goto unlock;
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goto unlock;
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}
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}
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tegra_sor_update(sor);
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value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
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value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
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value |= SOR_ENABLE;
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value |= SOR_ENABLE;
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tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
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tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
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tegra_sor_update(sor);
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tegra_dc_commit(dc);
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err = tegra_sor_attach(sor);
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err = tegra_sor_attach(sor);
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if (err < 0) {
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if (err < 0) {
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