phy: for 4.19
*) Add new PHY driver for GEN3 PCIe PHY on Renesas R-Car *) Add new PHY driver for PCIe PHY on Broadcom's Stingray SoC *) Enable battery charging in Mediatek T-PHY *) Switch to SPDX identifier in Marvell PHY drivers *) Fix compilation warning in phy-qcom-usb-hs.c Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJbVrx8AAoJEA5ceFyATYLZSEgP/RPdywh5LsefzKUl/I7X3Npz DGYOMC//4ezNSiRXZzzjTlGc4xr0sJiBtrw4ZTW6QsgebBl/TqVsBbXcv3l7rEGZ fVd67E1jPkhyVF9ov81Oq8Ae2j5XMHkj+0h5FgDK6ngz/ioMA032BHJdCWu8YLDc MgmxfMOVwrHdC7JZJ3UmXdgBD1eRbb9cD7nCR8LK/cW3ShTq6BxvHmRd9E2vXGbU P03ovDfhSQBiPx5nNBxBuCoT7XoT+4TNys8NkgbKJ4lqEwYKPHCA0ens7ybuzHtG R7a+yCyzpLAd3rpjZcBDCnjOnqyZqAmOC9MO/TjZqwdJQiAGmRCEFmOWmCqYPQN4 NBN8en26McBsUWeMNEUfnTIRJVmRlMruB1WhPkDAtRrJn/xMAFKIFvum5aO8z/fv o2JRhZtx19X4YkVS9ut//BIus3TnnTB1qveBBiuC54QO/9e0WoZwr1wMrFa2Hcif Pa16M2sYkXV1NgRhcY+TpltcG6fs3mZj13DxH4SKek+hfntk28omWAecsPVg902K QcGfimKJ6unf7FW4GtzGEjLu6e1gNJgp3FRaAknL3HKBckwYcuB1OBEqzKsGiA8n yZXhguRXm95ECi/emSONQC3ld4BlDI4xsqdfeqjxmGPI6Rrlsyv2ZQP38csfGjG+ W7G3paOMq80U4tVMFcjQ =V2N7 -----END PGP SIGNATURE----- Merge tag 'phy-for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 4.19 *) Add new PHY driver for GEN3 PCIe PHY on Renesas R-Car *) Add new PHY driver for PCIe PHY on Broadcom's Stingray SoC *) Enable battery charging in Mediatek T-PHY *) Switch to SPDX identifier in Marvell PHY drivers *) Fix compilation warning in phy-qcom-usb-hs.c Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>hifive-unleashed-5.1
Greg Kroah-Hartman
commit
668aee263b
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@ -0,0 +1,41 @@
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Broadcom Stingray PCIe PHY
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Required properties:
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- compatible: must be "brcm,sr-pcie-phy"
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- reg: base address and length of the PCIe SS register space
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- brcm,sr-cdru: phandle to the CDRU syscon node
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- brcm,sr-mhb: phandle to the MHB syscon node
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- #phy-cells: Must be 1, denotes the PHY index
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For PAXB based root complex, one can have a configuration of up to 8 PHYs
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PHY index goes from 0 to 7
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For the internal PAXC based root complex, PHY index is always 8
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Example:
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mhb: syscon@60401000 {
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compatible = "brcm,sr-mhb", "syscon";
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reg = <0 0x60401000 0 0x38c>;
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};
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cdru: syscon@6641d000 {
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compatible = "brcm,sr-cdru", "syscon";
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reg = <0 0x6641d000 0 0x400>;
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};
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pcie_phy: phy@40000000 {
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compatible = "brcm,sr-pcie-phy";
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reg = <0 0x40000000 0 0x800>;
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brcm,sr-cdru = <&cdru>;
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brcm,sr-mhb = <&mhb>;
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#phy-cells = <1>;
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};
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/* users of the PCIe PHY */
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pcie0: pcie@48000000 {
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...
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...
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phys = <&pcie_phy 0>;
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phy-names = "pcie-phy";
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};
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@ -47,6 +47,12 @@ Required properties (port (child) node):
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- PHY_TYPE_PCIE
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- PHY_TYPE_SATA
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Optional properties (PHY_TYPE_USB2 port (child) node):
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- mediatek,eye-src : u32, the value of slew rate calibrate
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- mediatek,eye-vrt : u32, the selection of VRT reference voltage
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- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
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- mediatek,bc12 : bool, enable BC12 of u2phy if support it
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Example:
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u3phy: usb-phy@11290000 {
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@ -12,7 +12,14 @@ Required properties:
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"qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
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"qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845.
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- reg: offset and length of register set for PHY's common serdes block.
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- reg:
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- For "qcom,sdm845-qmp-usb3-phy":
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- index 0: address and length of register set for PHY's common serdes
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block.
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- named register "dp_com" (using reg-names): address and length of the
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DP_COM control block.
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- For all others:
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- offset and length of register set for PHY's common serdes block.
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- #clock-cells: must be 1
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- Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
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@ -60,7 +67,10 @@ Required nodes:
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Required properties for child node:
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- reg: list of offset and length pairs of register sets for PHY blocks -
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tx, rx and pcs.
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- index 0: tx
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- index 1: rx
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- index 2: pcs
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- index 3: pcs_misc (optional)
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- #phy-cells: must be 0
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@ -0,0 +1,24 @@
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* Renesas R-Car generation 3 PCIe PHY
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This file provides information on what the device node for the R-Car
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generation 3 PCIe PHY contains.
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Required properties:
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- compatible: "renesas,r8a77980-pcie-phy" if the device is a part of the
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R8A77980 SoC.
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- reg: offset and length of the register block.
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- clocks: clock phandle and specifier pair.
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- power-domains: power domain phandle and specifier pair.
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- resets: reset phandle and specifier pair.
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- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
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Example (R-Car V3H):
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pcie-phy@e65d0000 {
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compatible = "renesas,r8a77980-pcie-phy";
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reg = <0 0xe65d0000 0 0x8000>;
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#phy-cells = <0>;
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clocks = <&cpg CPG_MOD 319>;
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power-domains = <&sysc 32>;
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resets = <&cpg 319>;
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};
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@ -10,6 +10,8 @@ Required properties:
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SoC.
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"renesas,usb2-phy-r8a77965" if the device is a part of an
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R8A77965 SoC.
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"renesas,usb2-phy-r8a77990" if the device is a part of an
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R8A77990 SoC.
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"renesas,usb2-phy-r8a77995" if the device is a part of an
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R8A77995 SoC.
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"renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device.
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@ -1647,7 +1647,8 @@ M: Chunfeng Yun <chunfeng.yun@mediatek.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: drivers/phy/mediatek/phy-mtk-tphy.c
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F: drivers/phy/mediatek/
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F: Documentation/devicetree/bindings/phy/phy-mtk-*
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ARM/MICREL KS8695 ARCHITECTURE
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M: Greg Ungerer <gerg@uclinux.org>
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@ -80,3 +80,13 @@ config PHY_BRCM_USB
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This driver is required by the USB XHCI, EHCI and OHCI
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drivers.
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If unsure, say N.
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config PHY_BCM_SR_PCIE
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tristate "Broadcom Stingray PCIe PHY driver"
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depends on OF && (ARCH_BCM_IPROC || COMPILE_TEST)
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select GENERIC_PHY
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select MFD_SYSCON
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default ARCH_BCM_IPROC
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help
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Enable this to support the Broadcom Stingray PCIe PHY
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If unsure, say N.
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@ -9,3 +9,5 @@ obj-$(CONFIG_PHY_BRCM_SATA) += phy-brcm-sata.o
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obj-$(CONFIG_PHY_BRCM_USB) += phy-brcm-usb-dvr.o
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phy-brcm-usb-dvr-objs := phy-brcm-usb.o phy-brcm-usb-init.o
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obj-$(CONFIG_PHY_BCM_SR_PCIE) += phy-bcm-sr-pcie.o
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@ -0,0 +1,305 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Broadcom
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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/* we have up to 8 PAXB based RC. The 9th one is always PAXC */
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#define SR_NR_PCIE_PHYS 9
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#define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
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#define PCIE_PIPEMUX_CFG_OFFSET 0x10c
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#define PCIE_PIPEMUX_SELECT_STRAP 0xf
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#define CDRU_STRAP_DATA_LSW_OFFSET 0x5c
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#define PCIE_PIPEMUX_SHIFT 19
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#define PCIE_PIPEMUX_MASK 0xf
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#define MHB_MEM_PW_PAXC_OFFSET 0x1c0
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#define MHB_PWR_ARR_POWERON 0x8
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#define MHB_PWR_ARR_POWEROK 0x4
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#define MHB_PWR_POWERON 0x2
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#define MHB_PWR_POWEROK 0x1
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#define MHB_PWR_STATUS_MASK (MHB_PWR_ARR_POWERON | \
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MHB_PWR_ARR_POWEROK | \
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MHB_PWR_POWERON | \
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MHB_PWR_POWEROK)
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struct sr_pcie_phy_core;
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/**
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* struct sr_pcie_phy - Stingray PCIe PHY
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*
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* @core: pointer to the Stingray PCIe PHY core control
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* @index: PHY index
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* @phy: pointer to the kernel PHY device
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*/
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struct sr_pcie_phy {
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struct sr_pcie_phy_core *core;
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unsigned int index;
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struct phy *phy;
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};
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/**
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* struct sr_pcie_phy_core - Stingray PCIe PHY core control
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*
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* @dev: pointer to device
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* @base: base register of PCIe SS
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* @cdru: regmap to the CDRU device
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* @mhb: regmap to the MHB device
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* @pipemux: pipemuex strap
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* @phys: array of PCIe PHYs
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*/
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struct sr_pcie_phy_core {
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struct device *dev;
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void __iomem *base;
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struct regmap *cdru;
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struct regmap *mhb;
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u32 pipemux;
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struct sr_pcie_phy phys[SR_NR_PCIE_PHYS];
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};
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/*
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* PCIe PIPEMUX lookup table
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*
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* Each array index represents a PIPEMUX strap setting
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* The array element represents a bitmap where a set bit means the PCIe
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* core and associated serdes has been enabled as RC and is available for use
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*/
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static const u8 pipemux_table[] = {
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/* PIPEMUX = 0, EP 1x16 */
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0x00,
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/* PIPEMUX = 1, EP 2x8 */
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0x00,
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/* PIPEMUX = 2, EP 4x4 */
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0x00,
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/* PIPEMUX = 3, RC 2x8, cores 0, 7 */
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0x81,
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/* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */
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0xc3,
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/* PIPEMUX = 5, RC 8x2, all 8 cores */
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0xff,
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/* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */
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0xcd,
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/* PIPEMUX = 7, RC 1x4 + 6x2, cores 0, 2, 3, 4, 5, 6, 7 */
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0xfd,
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/* PIPEMUX = 8, EP 1x8 + RC 4x2, cores 4, 5, 6, 7 */
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0xf0,
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/* PIPEMUX = 9, EP 1x8 + RC 2x4, cores 6, 7 */
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0xc0,
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/* PIPEMUX = 10, EP 2x4 + RC 2x4, cores 1, 6 */
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0x42,
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/* PIPEMUX = 11, EP 2x4 + RC 4x2, cores 2, 3, 4, 5 */
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0x3c,
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/* PIPEMUX = 12, EP 1x4 + RC 6x2, cores 2, 3, 4, 5, 6, 7 */
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0xfc,
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/* PIPEMUX = 13, RC 2x4 + RC 1x4 + 2x2, cores 2, 3, 6 */
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0x4c,
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};
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/*
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* Return true if the strap setting is valid
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*/
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static bool pipemux_strap_is_valid(u32 pipemux)
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{
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return !!(pipemux < ARRAY_SIZE(pipemux_table));
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}
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/*
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* Read the PCIe PIPEMUX from strap
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*/
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static u32 pipemux_strap_read(struct sr_pcie_phy_core *core)
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{
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u32 pipemux;
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/*
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* Read PIPEMUX configuration register to determine the pipemux setting
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*
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* In the case when the value indicates using HW strap, fall back to
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* use HW strap
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*/
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pipemux = readl(core->base + PCIE_PIPEMUX_CFG_OFFSET);
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pipemux &= PCIE_PIPEMUX_MASK;
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if (pipemux == PCIE_PIPEMUX_SELECT_STRAP) {
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regmap_read(core->cdru, CDRU_STRAP_DATA_LSW_OFFSET, &pipemux);
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pipemux >>= PCIE_PIPEMUX_SHIFT;
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pipemux &= PCIE_PIPEMUX_MASK;
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}
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return pipemux;
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}
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/*
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* Given a PIPEMUX strap and PCIe core index, this function returns true if the
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* PCIe core needs to be enabled
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*/
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static bool pcie_core_is_for_rc(struct sr_pcie_phy *phy)
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{
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struct sr_pcie_phy_core *core = phy->core;
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unsigned int core_idx = phy->index;
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return !!((pipemux_table[core->pipemux] >> core_idx) & 0x1);
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}
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static int sr_pcie_phy_init(struct phy *p)
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{
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struct sr_pcie_phy *phy = phy_get_drvdata(p);
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/*
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* Check whether this PHY is for root complex or not. If yes, return
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* zero so the host driver can proceed to enumeration. If not, return
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* an error and that will force the host driver to bail out
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*/
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if (pcie_core_is_for_rc(phy))
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return 0;
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return -ENODEV;
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}
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static int sr_paxc_phy_init(struct phy *p)
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{
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struct sr_pcie_phy *phy = phy_get_drvdata(p);
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struct sr_pcie_phy_core *core = phy->core;
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unsigned int core_idx = phy->index;
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u32 val;
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if (core_idx != SR_PAXC_PHY_IDX)
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return -EINVAL;
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regmap_read(core->mhb, MHB_MEM_PW_PAXC_OFFSET, &val);
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if ((val & MHB_PWR_STATUS_MASK) != MHB_PWR_STATUS_MASK) {
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dev_err(core->dev, "PAXC is not powered up\n");
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return -ENODEV;
|
||||
}
|
||||
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||||
return 0;
|
||||
}
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|
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static const struct phy_ops sr_pcie_phy_ops = {
|
||||
.init = sr_pcie_phy_init,
|
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.owner = THIS_MODULE,
|
||||
};
|
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|
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static const struct phy_ops sr_paxc_phy_ops = {
|
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.init = sr_paxc_phy_init,
|
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.owner = THIS_MODULE,
|
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};
|
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|
||||
static struct phy *sr_pcie_phy_xlate(struct device *dev,
|
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struct of_phandle_args *args)
|
||||
{
|
||||
struct sr_pcie_phy_core *core;
|
||||
int phy_idx;
|
||||
|
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core = dev_get_drvdata(dev);
|
||||
if (!core)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
phy_idx = args->args[0];
|
||||
|
||||
if (WARN_ON(phy_idx >= SR_NR_PCIE_PHYS))
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return ERR_PTR(-ENODEV);
|
||||
|
||||
return core->phys[phy_idx].phy;
|
||||
}
|
||||
|
||||
static int sr_pcie_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->of_node;
|
||||
struct sr_pcie_phy_core *core;
|
||||
struct resource *res;
|
||||
struct phy_provider *provider;
|
||||
unsigned int phy_idx = 0;
|
||||
|
||||
core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
|
||||
if (!core)
|
||||
return -ENOMEM;
|
||||
|
||||
core->dev = dev;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
core->base = devm_ioremap_resource(core->dev, res);
|
||||
if (IS_ERR(core->base))
|
||||
return PTR_ERR(core->base);
|
||||
|
||||
core->cdru = syscon_regmap_lookup_by_phandle(node, "brcm,sr-cdru");
|
||||
if (IS_ERR(core->cdru)) {
|
||||
dev_err(core->dev, "unable to find CDRU device\n");
|
||||
return PTR_ERR(core->cdru);
|
||||
}
|
||||
|
||||
core->mhb = syscon_regmap_lookup_by_phandle(node, "brcm,sr-mhb");
|
||||
if (IS_ERR(core->mhb)) {
|
||||
dev_err(core->dev, "unable to find MHB device\n");
|
||||
return PTR_ERR(core->mhb);
|
||||
}
|
||||
|
||||
/* read the PCIe PIPEMUX strap setting */
|
||||
core->pipemux = pipemux_strap_read(core);
|
||||
if (!pipemux_strap_is_valid(core->pipemux)) {
|
||||
dev_err(core->dev, "invalid PCIe PIPEMUX strap %u\n",
|
||||
core->pipemux);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
for (phy_idx = 0; phy_idx < SR_NR_PCIE_PHYS; phy_idx++) {
|
||||
struct sr_pcie_phy *p = &core->phys[phy_idx];
|
||||
const struct phy_ops *ops;
|
||||
|
||||
if (phy_idx == SR_PAXC_PHY_IDX)
|
||||
ops = &sr_paxc_phy_ops;
|
||||
else
|
||||
ops = &sr_pcie_phy_ops;
|
||||
|
||||
p->phy = devm_phy_create(dev, NULL, ops);
|
||||
if (IS_ERR(p->phy)) {
|
||||
dev_err(dev, "failed to create PCIe PHY\n");
|
||||
return PTR_ERR(p->phy);
|
||||
}
|
||||
|
||||
p->core = core;
|
||||
p->index = phy_idx;
|
||||
phy_set_drvdata(p->phy, p);
|
||||
}
|
||||
|
||||
dev_set_drvdata(dev, core);
|
||||
|
||||
provider = devm_of_phy_provider_register(dev, sr_pcie_phy_xlate);
|
||||
if (IS_ERR(provider)) {
|
||||
dev_err(dev, "failed to register PHY provider\n");
|
||||
return PTR_ERR(provider);
|
||||
}
|
||||
|
||||
dev_info(dev, "Stingray PCIe PHY driver initialized\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id sr_pcie_phy_match_table[] = {
|
||||
{ .compatible = "brcm,sr-pcie-phy" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sr_pcie_phy_match_table);
|
||||
|
||||
static struct platform_driver sr_pcie_phy_driver = {
|
||||
.driver = {
|
||||
.name = "sr-pcie-phy",
|
||||
.of_match_table = sr_pcie_phy_match_table,
|
||||
},
|
||||
.probe = sr_pcie_phy_probe,
|
||||
};
|
||||
module_platform_driver(sr_pcie_phy_driver);
|
||||
|
||||
MODULE_AUTHOR("Ray Jui <ray.jui@broadcom.com>");
|
||||
MODULE_DESCRIPTION("Broadcom Stingray PCIe PHY driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -1,13 +1,10 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Marvell Berlin SATA PHY driver
|
||||
*
|
||||
* Copyright (C) 2014 Marvell Technology Group Ltd.
|
||||
*
|
||||
* Antoine Ténart <antoine.tenart@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
|
|
|
|||
|
|
@ -1,12 +1,9 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2014 Marvell Technology Group Ltd.
|
||||
*
|
||||
* Antoine Tenart <antoine.tenart@free-electrons.com>
|
||||
* Jisheng Zhang <jszhang@marvell.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
|
|
|
|||
|
|
@ -1,11 +1,8 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017 Marvell
|
||||
*
|
||||
* Antoine Tenart <antoine.tenart@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# Makefile for the phy drivers.
|
||||
#
|
||||
|
|
|
|||
|
|
@ -1,16 +1,8 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2015 MediaTek Inc.
|
||||
* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
|
@ -50,6 +42,12 @@
|
|||
#define PA0_RG_U2PLL_FORCE_ON BIT(15)
|
||||
#define PA0_RG_USB20_INTR_EN BIT(5)
|
||||
|
||||
#define U3P_USBPHYACR1 0x004
|
||||
#define PA1_RG_VRT_SEL GENMASK(14, 12)
|
||||
#define PA1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12)
|
||||
#define PA1_RG_TERM_SEL GENMASK(10, 8)
|
||||
#define PA1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
|
||||
|
||||
#define U3P_USBPHYACR2 0x008
|
||||
#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
|
||||
|
||||
|
|
@ -103,6 +101,9 @@
|
|||
#define P2C_RG_AVALID BIT(2)
|
||||
#define P2C_RG_IDDIG BIT(1)
|
||||
|
||||
#define U3P_U2PHYBC12C 0x080
|
||||
#define P2C_RG_CHGDT_EN BIT(0)
|
||||
|
||||
#define U3P_U3_CHIP_GPIO_CTLD 0x0c
|
||||
#define P3C_REG_IP_SW_RST BIT(31)
|
||||
#define P3C_MCU_BUS_CK_GATE_EN BIT(30)
|
||||
|
|
@ -296,6 +297,10 @@ struct mtk_phy_instance {
|
|||
struct clk *ref_clk; /* reference clock of anolog phy */
|
||||
u32 index;
|
||||
u8 type;
|
||||
int eye_src;
|
||||
int eye_vrt;
|
||||
int eye_term;
|
||||
bool bc12_en;
|
||||
};
|
||||
|
||||
struct mtk_tphy {
|
||||
|
|
@ -320,6 +325,10 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
|
|||
int fm_out;
|
||||
u32 tmp;
|
||||
|
||||
/* use force value */
|
||||
if (instance->eye_src)
|
||||
return;
|
||||
|
||||
/* enable USB ring oscillator */
|
||||
tmp = readl(com + U3P_USBPHYACR5);
|
||||
tmp |= PA5_RG_U2_HSTX_SRCAL_EN;
|
||||
|
|
@ -826,6 +835,61 @@ static void phy_v2_banks_init(struct mtk_tphy *tphy,
|
|||
}
|
||||
}
|
||||
|
||||
static void phy_parse_property(struct mtk_tphy *tphy,
|
||||
struct mtk_phy_instance *instance)
|
||||
{
|
||||
struct device *dev = &instance->phy->dev;
|
||||
|
||||
if (instance->type != PHY_TYPE_USB2)
|
||||
return;
|
||||
|
||||
instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");
|
||||
device_property_read_u32(dev, "mediatek,eye-src",
|
||||
&instance->eye_src);
|
||||
device_property_read_u32(dev, "mediatek,eye-vrt",
|
||||
&instance->eye_vrt);
|
||||
device_property_read_u32(dev, "mediatek,eye-term",
|
||||
&instance->eye_term);
|
||||
dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d\n",
|
||||
instance->bc12_en, instance->eye_src,
|
||||
instance->eye_vrt, instance->eye_term);
|
||||
}
|
||||
|
||||
static void u2_phy_props_set(struct mtk_tphy *tphy,
|
||||
struct mtk_phy_instance *instance)
|
||||
{
|
||||
struct u2phy_banks *u2_banks = &instance->u2_banks;
|
||||
void __iomem *com = u2_banks->com;
|
||||
u32 tmp;
|
||||
|
||||
if (instance->bc12_en) {
|
||||
tmp = readl(com + U3P_U2PHYBC12C);
|
||||
tmp |= P2C_RG_CHGDT_EN; /* BC1.2 path Enable */
|
||||
writel(tmp, com + U3P_U2PHYBC12C);
|
||||
}
|
||||
|
||||
if (instance->eye_src) {
|
||||
tmp = readl(com + U3P_USBPHYACR5);
|
||||
tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
|
||||
tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src);
|
||||
writel(tmp, com + U3P_USBPHYACR5);
|
||||
}
|
||||
|
||||
if (instance->eye_vrt) {
|
||||
tmp = readl(com + U3P_USBPHYACR1);
|
||||
tmp &= ~PA1_RG_VRT_SEL;
|
||||
tmp |= PA1_RG_VRT_SEL_VAL(instance->eye_vrt);
|
||||
writel(tmp, com + U3P_USBPHYACR1);
|
||||
}
|
||||
|
||||
if (instance->eye_term) {
|
||||
tmp = readl(com + U3P_USBPHYACR1);
|
||||
tmp &= ~PA1_RG_TERM_SEL;
|
||||
tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term);
|
||||
writel(tmp, com + U3P_USBPHYACR1);
|
||||
}
|
||||
}
|
||||
|
||||
static int mtk_phy_init(struct phy *phy)
|
||||
{
|
||||
struct mtk_phy_instance *instance = phy_get_drvdata(phy);
|
||||
|
|
@ -847,6 +911,7 @@ static int mtk_phy_init(struct phy *phy)
|
|||
switch (instance->type) {
|
||||
case PHY_TYPE_USB2:
|
||||
u2_phy_instance_init(tphy, instance);
|
||||
u2_phy_props_set(tphy, instance);
|
||||
break;
|
||||
case PHY_TYPE_USB3:
|
||||
u3_phy_instance_init(tphy, instance);
|
||||
|
|
@ -959,6 +1024,8 @@ static struct phy *mtk_phy_xlate(struct device *dev,
|
|||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
phy_parse_property(tphy, instance);
|
||||
|
||||
return instance->phy;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -55,6 +55,7 @@ static int qcom_usb_hs_phy_set_mode(struct phy *phy, enum phy_mode mode)
|
|||
case PHY_MODE_USB_OTG:
|
||||
case PHY_MODE_USB_HOST:
|
||||
val |= ULPI_INT_IDGRD;
|
||||
/* fall through */
|
||||
case PHY_MODE_USB_DEVICE:
|
||||
val |= ULPI_INT_SESS_VALID;
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -8,6 +8,13 @@ config PHY_RCAR_GEN2
|
|||
help
|
||||
Support for USB PHY found on Renesas R-Car generation 2 SoCs.
|
||||
|
||||
config PHY_RCAR_GEN3_PCIE
|
||||
tristate "Renesas R-Car generation 3 PCIe PHY driver"
|
||||
depends on ARCH_RENESAS
|
||||
select GENERIC_PHY
|
||||
help
|
||||
Support for the PCIe PHY found on Renesas R-Car generation 3 SoCs.
|
||||
|
||||
config PHY_RCAR_GEN3_USB2
|
||||
tristate "Renesas R-Car generation 3 USB 2.0 PHY driver"
|
||||
depends on ARCH_RENESAS
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
|
||||
obj-$(CONFIG_PHY_RCAR_GEN3_PCIE) += phy-rcar-gen3-pcie.o
|
||||
obj-$(CONFIG_PHY_RCAR_GEN3_USB2) += phy-rcar-gen3-usb2.o
|
||||
obj-$(CONFIG_PHY_RCAR_GEN3_USB3) += phy-rcar-gen3-usb3.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,151 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas R-Car Gen3 PCIe PHY driver
|
||||
*
|
||||
* Copyright (C) 2018 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#define PHY_CTRL 0x4000 /* R8A77980 only */
|
||||
|
||||
/* PHY control register (PHY_CTRL) */
|
||||
#define PHY_CTRL_PHY_PWDN BIT(2)
|
||||
|
||||
struct rcar_gen3_phy {
|
||||
struct phy *phy;
|
||||
spinlock_t lock;
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
static void rcar_gen3_phy_pcie_modify_reg(struct phy *p, unsigned int reg,
|
||||
u32 clear, u32 set)
|
||||
{
|
||||
struct rcar_gen3_phy *phy = phy_get_drvdata(p);
|
||||
void __iomem *base = phy->base;
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
|
||||
spin_lock_irqsave(&phy->lock, flags);
|
||||
|
||||
value = readl(base + reg);
|
||||
value &= ~clear;
|
||||
value |= set;
|
||||
writel(value, base + reg);
|
||||
|
||||
spin_unlock_irqrestore(&phy->lock, flags);
|
||||
}
|
||||
|
||||
static int r8a77980_phy_pcie_power_on(struct phy *p)
|
||||
{
|
||||
/* Power on the PCIe PHY */
|
||||
rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, PHY_CTRL_PHY_PWDN, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int r8a77980_phy_pcie_power_off(struct phy *p)
|
||||
{
|
||||
/* Power off the PCIe PHY */
|
||||
rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, 0, PHY_CTRL_PHY_PWDN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops r8a77980_phy_pcie_ops = {
|
||||
.power_on = r8a77980_phy_pcie_power_on,
|
||||
.power_off = r8a77980_phy_pcie_power_off,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static const struct of_device_id rcar_gen3_phy_pcie_match_table[] = {
|
||||
{ .compatible = "renesas,r8a77980-pcie-phy" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rcar_gen3_phy_pcie_match_table);
|
||||
|
||||
static int rcar_gen3_phy_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct phy_provider *provider;
|
||||
struct rcar_gen3_phy *phy;
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
int error;
|
||||
|
||||
if (!dev->of_node) {
|
||||
dev_err(dev,
|
||||
"This driver must only be instantiated from the device tree\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
|
||||
if (!phy)
|
||||
return -ENOMEM;
|
||||
|
||||
spin_lock_init(&phy->lock);
|
||||
|
||||
phy->base = base;
|
||||
|
||||
/*
|
||||
* devm_phy_create() will call pm_runtime_enable(&phy->dev);
|
||||
* And then, phy-core will manage runtime PM for this device.
|
||||
*/
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
phy->phy = devm_phy_create(dev, NULL, &r8a77980_phy_pcie_ops);
|
||||
if (IS_ERR(phy->phy)) {
|
||||
dev_err(dev, "Failed to create PCIe PHY\n");
|
||||
error = PTR_ERR(phy->phy);
|
||||
goto error;
|
||||
}
|
||||
phy_set_drvdata(phy->phy, phy);
|
||||
|
||||
provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
if (IS_ERR(provider)) {
|
||||
dev_err(dev, "Failed to register PHY provider\n");
|
||||
error = PTR_ERR(provider);
|
||||
goto error;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
error:
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
static int rcar_gen3_phy_pcie_remove(struct platform_device *pdev)
|
||||
{
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
static struct platform_driver rcar_gen3_phy_driver = {
|
||||
.driver = {
|
||||
.name = "phy_rcar_gen3_pcie",
|
||||
.of_match_table = rcar_gen3_phy_pcie_match_table,
|
||||
},
|
||||
.probe = rcar_gen3_phy_pcie_probe,
|
||||
.remove = rcar_gen3_phy_pcie_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(rcar_gen3_phy_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("Renesas R-Car Gen3 PCIe PHY");
|
||||
MODULE_AUTHOR("Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>");
|
||||
Loading…
Reference in New Issue