drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON
LSPCON chips can generate YCBCR outputs, if asked nicely :). In order to generate YCBCR 4:2:0 outputs, a source must: - send YCBCR 4:4:4 signals to LSPCON - program color space as 4:2:0 in AVI infoframes Whereas for YCBCR 4:4:4 outputs, the source must: - send YCBCR 4:4:4 signals to LSPCON - program color space as 4:4:4 in AVI infoframes So for both 4:2:0 as well as 4:4:4 outputs, we are driving the pipe for YCBCR 4:4:4 output, but AVI infoframe's color space information indicates LSPCON FW to start scaling down from YCBCR 4:4:4 and generate YCBCR 4:2:0 output. As the scaling is done by LSPCON device, we need not to reserve a scaler for 4:2:0 outputs. V2: rebase V3: Addressed review comments from Ville - add enum crtc_output_format instead of bool ycbcr420 - use crtc_output_format=4:4:4 for modeset of LSPCON 4:2:0 output cases in this way we will have YCBCR 4:4:4 framework ready (except the ABI part) V4: Added r-b from Maarten (for v3) Addressed review comments from Ville: - Do not add a non-atomic state variable to determine lspcon output. Instead add bool in CRTC state to indicate lspcon based scaling. V5: Addressed review comments from Ville: - Change the state bool name from external scaling to something more relavent. - Keep the info and adjusted_mode structures const. - use crtc_state instead of pipe_config. - Push all the config change into lspcon_ycbcr420_config function. V6: Rebase, small changes to accommodate changes in patch 2. V7: Fixed checkpatch warnings for alignment V8: Rebase PS: Ignored following warnings to match the current formatting: drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON -:53: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #53: FILE: drivers/gpu/drm/i915/i915_reg.h:8721: +#define TRANS_MSA_SAMPLING_444 (2<<1) ^ -:54: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #54: FILE: drivers/gpu/drm/i915/i915_reg.h:8722: +#define TRANS_MSA_CLRSP_YCBCR (2<<3) V9: Rebase V10: Rebase V11: Rebase Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1539325394-20788-8-git-send-email-shashank.sharma@intel.com
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@ -9229,6 +9229,8 @@ enum skl_power_gate {
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#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
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#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
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#define TRANS_MSA_SYNC_CLK (1 << 0)
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#define TRANS_MSA_SYNC_CLK (1 << 0)
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#define TRANS_MSA_SAMPLING_444 (2 << 1)
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#define TRANS_MSA_CLRSP_YCBCR (2 << 3)
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#define TRANS_MSA_6_BPC (0 << 5)
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#define TRANS_MSA_6_BPC (0 << 5)
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#define TRANS_MSA_8_BPC (1 << 5)
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#define TRANS_MSA_8_BPC (1 << 5)
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#define TRANS_MSA_10_BPC (2 << 5)
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#define TRANS_MSA_10_BPC (2 << 5)
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@ -1784,6 +1784,13 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
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break;
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break;
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}
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}
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/*
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* As per DP 1.2 spec section 2.3.4.3 while sending
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* YCBCR 444 signals we should program MSA MISC1/0 fields with
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* colorspace information. The output colorspace encoding is BT601.
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*/
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if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
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temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
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I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
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I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
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}
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}
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@ -7797,6 +7797,8 @@ static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
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enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
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pipe_config->lspcon_downsampling = false;
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if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
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if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
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u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
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u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
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@ -7814,6 +7816,16 @@ static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
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else
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else
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output = INTEL_OUTPUT_FORMAT_YCBCR420;
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output = INTEL_OUTPUT_FORMAT_YCBCR420;
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} else {
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} else {
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/*
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* Currently there is no interface defined to
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* check user preference between RGB/YCBCR444
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* or YCBCR420. So the only possible case for
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* YCBCR444 usage is driving YCBCR420 output
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* with LSPCON, when pipe is configured for
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* YCBCR444 output and LSPCON takes care of
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* downsampling it.
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*/
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pipe_config->lspcon_downsampling = true;
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output = INTEL_OUTPUT_FORMAT_YCBCR444;
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output = INTEL_OUTPUT_FORMAT_YCBCR444;
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}
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}
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}
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}
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@ -2074,6 +2074,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
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struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
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struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
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enum port port = encoder->port;
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enum port port = encoder->port;
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struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
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struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
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struct intel_connector *intel_connector = intel_dp->attached_connector;
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struct intel_connector *intel_connector = intel_dp->attached_connector;
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@ -2086,6 +2087,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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pipe_config->has_pch_encoder = true;
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pipe_config->has_pch_encoder = true;
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pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
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pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
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if (lspcon->active)
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lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
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pipe_config->has_drrs = false;
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pipe_config->has_drrs = false;
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if (IS_G4X(dev_priv) || port == PORT_A)
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if (IS_G4X(dev_priv) || port == PORT_A)
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pipe_config->has_audio = false;
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pipe_config->has_audio = false;
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@ -908,6 +908,9 @@ struct intel_crtc_state {
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/* Output format RGB/YCBCR etc */
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/* Output format RGB/YCBCR etc */
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enum intel_output_format output_format;
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enum intel_output_format output_format;
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/* Output down scaling is done in LSPCON device */
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bool lspcon_downsampling;
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};
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};
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struct intel_crtc {
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struct intel_crtc {
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@ -2225,6 +2228,8 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
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const struct drm_connector_state *conn_state);
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const struct drm_connector_state *conn_state);
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bool lspcon_infoframe_enabled(struct intel_encoder *encoder,
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bool lspcon_infoframe_enabled(struct intel_encoder *encoder,
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const struct intel_crtc_state *pipe_config);
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const struct intel_crtc_state *pipe_config);
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void lspcon_ycbcr420_config(struct drm_connector *connector,
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struct intel_crtc_state *crtc_state);
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/* intel_pipe_crc.c */
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/* intel_pipe_crc.c */
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#ifdef CONFIG_DEBUG_FS
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#ifdef CONFIG_DEBUG_FS
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@ -180,6 +180,21 @@ static bool lspcon_wake_native_aux_ch(struct intel_lspcon *lspcon)
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return true;
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return true;
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}
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}
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void lspcon_ycbcr420_config(struct drm_connector *connector,
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struct intel_crtc_state *crtc_state)
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{
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const struct drm_display_info *info = &connector->display_info;
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const struct drm_display_mode *adjusted_mode =
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&crtc_state->base.adjusted_mode;
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if (drm_mode_is_420_only(info, adjusted_mode) &&
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connector->ycbcr_420_allowed) {
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crtc_state->port_clock /= 2;
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crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
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crtc_state->lspcon_downsampling = true;
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}
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}
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static bool lspcon_probe(struct intel_lspcon *lspcon)
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static bool lspcon_probe(struct intel_lspcon *lspcon)
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{
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{
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int retry;
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int retry;
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@ -464,6 +479,15 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
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return;
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return;
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}
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}
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if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
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if (crtc_state->lspcon_downsampling)
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frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
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else
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frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
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} else {
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frame.avi.colorspace = HDMI_COLORSPACE_RGB;
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}
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drm_hdmi_avi_infoframe_quant_range(&frame.avi, mode,
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drm_hdmi_avi_infoframe_quant_range(&frame.avi, mode,
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crtc_state->limited_color_range ?
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crtc_state->limited_color_range ?
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HDMI_QUANTIZATION_RANGE_LIMITED :
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HDMI_QUANTIZATION_RANGE_LIMITED :
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@ -517,6 +541,7 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port)
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struct intel_lspcon *lspcon = &intel_dig_port->lspcon;
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struct intel_lspcon *lspcon = &intel_dig_port->lspcon;
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struct drm_device *dev = intel_dig_port->base.base.dev;
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struct drm_device *dev = intel_dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_connector *connector = &dp->attached_connector->base;
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if (!HAS_LSPCON(dev_priv)) {
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if (!HAS_LSPCON(dev_priv)) {
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DRM_ERROR("LSPCON is not supported on this platform\n");
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DRM_ERROR("LSPCON is not supported on this platform\n");
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return false;
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return false;
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}
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}
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connector->ycbcr_420_allowed = true;
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lspcon->active = true;
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lspcon->active = true;
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DRM_DEBUG_KMS("Success: LSPCON init\n");
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DRM_DEBUG_KMS("Success: LSPCON init\n");
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return true;
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return true;
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