Merge remote-tracking branches 'asoc/topic/samsung', 'asoc/topic/sgtl5000', 'asoc/topic/stm32', 'asoc/topic/sunxi' and 'asoc/topic/tas571x' into asoc-next
Mark Brown
commit
668f21b180
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@ -37,7 +37,7 @@ VDDIO 1.8V 2.5V 3.3V
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Example:
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codec: sgtl5000@0a {
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codec: sgtl5000@a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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clocks = <&clks 150>;
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@ -10,13 +10,21 @@ Required properties:
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- reg: Base address and size of SAI common register set.
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- clocks: Must contain phandle and clock specifier pairs for each entry
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in clock-names.
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- clock-names: Must contain "x8k" and "x11k"
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- clock-names: Must contain "pclk" "x8k" and "x11k"
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"pclk": Clock which feeds the peripheral bus interface.
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Mandatory for "st,stm32h7-sai" compatible.
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Not used for "st,stm32f4-sai" compatible.
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"x8k": SAI parent clock for sampling rates multiple of 8kHz.
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"x11k": SAI parent clock for sampling rates multiple of 11.025kHz.
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- interrupts: cpu DAI interrupt line shared by SAI sub-blocks
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Optional properties:
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- resets: Reference to a reset controller asserting the SAI
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- st,sync: specify synchronization mode.
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By default SAI sub-block is in asynchronous mode.
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This property sets SAI sub-block as slave of another SAI sub-block.
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Must contain the phandle and index of the sai sub-block providing
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the synchronization.
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SAI subnodes:
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Two subnodes corresponding to SAI sub-block instances A et B can be defined.
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@ -52,8 +60,8 @@ sai1: sai1@40015800 {
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#size-cells = <1>;
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ranges = <0 0x40015800 0x400>;
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reg = <0x40015800 0x4>;
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clocks = <&rcc PLL1_Q>, <&rcc PLL2_P>;
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clock-names = "x8k", "x11k";
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clocks = <&rcc SAI1_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>;
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clock-names = "pclk", "x8k", "x11k";
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interrupts = <87>;
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sai1a: audio-controller@40015804 {
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@ -697,7 +697,8 @@ static int tas571x_i2c_probe(struct i2c_client *client,
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return PTR_ERR(priv->mclk);
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}
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BUG_ON(priv->chip->num_supply_names > TAS571X_MAX_SUPPLIES);
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if (WARN_ON(priv->chip->num_supply_names > TAS571X_MAX_SUPPLIES))
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return -EINVAL;
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for (i = 0; i < priv->chip->num_supply_names; i++)
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priv->supplies[i].supply = priv->chip->supply_names[i];
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@ -1099,6 +1099,7 @@ static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev,
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i2s->pdev = pdev;
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i2s->pri_dai = NULL;
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i2s->sec_dai = NULL;
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i2s->i2s_dai_drv.id = 1;
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i2s->i2s_dai_drv.symmetric_rates = 1;
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i2s->i2s_dai_drv.probe = samsung_i2s_dai_probe;
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i2s->i2s_dai_drv.remove = samsung_i2s_dai_remove;
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@ -1111,10 +1112,13 @@ static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev,
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i2s->i2s_dai_drv.playback.formats = SAMSUNG_I2S_FMTS;
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if (!sec) {
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i2s->i2s_dai_drv.name = SAMSUNG_I2S_DAI;
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i2s->i2s_dai_drv.capture.channels_min = 1;
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i2s->i2s_dai_drv.capture.channels_max = 2;
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i2s->i2s_dai_drv.capture.rates = i2s_dai_data->pcm_rates;
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i2s->i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS;
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} else {
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i2s->i2s_dai_drv.name = SAMSUNG_I2S_DAI_SEC;
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}
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return i2s;
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}
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@ -13,6 +13,9 @@
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#ifndef __SND_SOC_SAMSUNG_I2S_H
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#define __SND_SOC_SAMSUNG_I2S_H
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#define SAMSUNG_I2S_DAI "samsung-i2s"
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#define SAMSUNG_I2S_DAI_SEC "samsung-i2s-sec"
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#define SAMSUNG_I2S_DIV_BCLK 1
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#define SAMSUNG_I2S_RCLKSRC_0 0
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@ -383,6 +383,7 @@ static struct snd_soc_dai_link tm2_dai_links[] = {
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{
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.name = "WM5110 AIF1",
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.stream_name = "HiFi Primary",
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.cpu_dai_name = SAMSUNG_I2S_DAI,
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.codec_dai_name = "wm5110-aif1",
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.ops = &tm2_aif1_ops,
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.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
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@ -390,6 +391,7 @@ static struct snd_soc_dai_link tm2_dai_links[] = {
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}, {
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.name = "WM5110 Voice",
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.stream_name = "Voice call",
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.cpu_dai_name = SAMSUNG_I2S_DAI,
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.codec_dai_name = "wm5110-aif2",
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.ops = &tm2_aif2_ops,
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.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
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@ -398,6 +400,7 @@ static struct snd_soc_dai_link tm2_dai_links[] = {
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}, {
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.name = "WM5110 BT",
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.stream_name = "Bluetooth",
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.cpu_dai_name = SAMSUNG_I2S_DAI,
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.codec_dai_name = "wm5110-aif3",
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.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
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SND_SOC_DAIFMT_CBM_CFM,
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@ -436,8 +439,7 @@ static int tm2_probe(struct platform_device *pdev)
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snd_soc_card_set_drvdata(card, priv);
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card->dev = dev;
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priv->gpio_mic_bias = devm_gpiod_get(dev, "mic-bias",
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GPIOF_OUT_INIT_LOW);
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priv->gpio_mic_bias = devm_gpiod_get(dev, "mic-bias", GPIOD_OUT_HIGH);
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if (IS_ERR(priv->gpio_mic_bias)) {
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dev_err(dev, "Failed to get mic bias gpio\n");
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return PTR_ERR(priv->gpio_mic_bias);
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@ -477,7 +479,6 @@ static int tm2_probe(struct platform_device *pdev)
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}
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for (i = 0; i < card->num_links; i++) {
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card->dai_link[i].cpu_dai_name = NULL;
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card->dai_link[i].cpu_name = NULL;
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card->dai_link[i].platform_name = NULL;
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card->dai_link[i].codec_of_node = codec_dai_node;
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@ -16,6 +16,7 @@
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* details.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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@ -27,6 +28,16 @@
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#include "stm32_sai.h"
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static LIST_HEAD(sync_providers);
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static DEFINE_MUTEX(sync_mutex);
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struct sync_provider {
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struct list_head link;
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struct device_node *node;
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int (*sync_conf)(void *data, int synco);
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void *data;
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};
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static const struct stm32_sai_conf stm32_sai_conf_f4 = {
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.version = SAI_STM32F4,
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};
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@ -41,23 +52,143 @@ static const struct of_device_id stm32_sai_ids[] = {
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{}
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};
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static int stm32_sai_sync_conf_client(struct stm32_sai_data *sai, int synci)
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{
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int ret;
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/* Enable peripheral clock to allow GCR register access */
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ret = clk_prepare_enable(sai->pclk);
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if (ret) {
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dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret);
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return ret;
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}
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writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base);
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clk_disable_unprepare(sai->pclk);
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return 0;
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}
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static int stm32_sai_sync_conf_provider(void *data, int synco)
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{
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struct stm32_sai_data *sai = (struct stm32_sai_data *)data;
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u32 prev_synco;
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int ret;
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/* Enable peripheral clock to allow GCR register access */
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ret = clk_prepare_enable(sai->pclk);
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if (ret) {
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dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret);
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return ret;
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}
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dev_dbg(&sai->pdev->dev, "Set %s%s as synchro provider\n",
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sai->pdev->dev.of_node->name,
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synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
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prev_synco = FIELD_GET(SAI_GCR_SYNCOUT_MASK, readl_relaxed(sai->base));
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if (prev_synco != STM_SAI_SYNC_OUT_NONE && synco != prev_synco) {
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dev_err(&sai->pdev->dev, "%s%s already set as sync provider\n",
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sai->pdev->dev.of_node->name,
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prev_synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
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clk_disable_unprepare(sai->pclk);
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return -EINVAL;
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}
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writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base);
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clk_disable_unprepare(sai->pclk);
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return 0;
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}
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static int stm32_sai_set_sync_provider(struct device_node *np, int synco)
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{
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struct sync_provider *provider;
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int ret;
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mutex_lock(&sync_mutex);
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list_for_each_entry(provider, &sync_providers, link) {
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if (provider->node == np) {
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ret = provider->sync_conf(provider->data, synco);
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mutex_unlock(&sync_mutex);
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return ret;
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}
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}
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mutex_unlock(&sync_mutex);
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/* SAI sync provider not found */
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return -ENODEV;
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}
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static int stm32_sai_set_sync(struct stm32_sai_data *sai,
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struct device_node *np_provider,
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int synco, int synci)
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{
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int ret;
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/* Configure sync client */
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stm32_sai_sync_conf_client(sai, synci);
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/* Configure sync provider */
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ret = stm32_sai_set_sync_provider(np_provider, synco);
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return ret;
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}
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static int stm32_sai_sync_add_provider(struct platform_device *pdev,
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void *data)
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{
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struct sync_provider *sp;
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sp = devm_kzalloc(&pdev->dev, sizeof(*sp), GFP_KERNEL);
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if (!sp)
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return -ENOMEM;
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sp->node = of_node_get(pdev->dev.of_node);
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sp->data = data;
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sp->sync_conf = &stm32_sai_sync_conf_provider;
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mutex_lock(&sync_mutex);
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list_add(&sp->link, &sync_providers);
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mutex_unlock(&sync_mutex);
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return 0;
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}
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static void stm32_sai_sync_del_provider(struct device_node *np)
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{
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struct sync_provider *sp;
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mutex_lock(&sync_mutex);
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list_for_each_entry(sp, &sync_providers, link) {
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if (sp->node == np) {
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list_del(&sp->link);
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of_node_put(sp->node);
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break;
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}
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}
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mutex_unlock(&sync_mutex);
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}
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static int stm32_sai_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct stm32_sai_data *sai;
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struct reset_control *rst;
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struct resource *res;
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void __iomem *base;
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const struct of_device_id *of_id;
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int ret;
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sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
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if (!sai)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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sai->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(sai->base))
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return PTR_ERR(sai->base);
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of_id = of_match_device(stm32_sai_ids, &pdev->dev);
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if (of_id)
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@ -65,6 +196,14 @@ static int stm32_sai_probe(struct platform_device *pdev)
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else
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return -EINVAL;
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if (!STM_SAI_IS_F4(sai)) {
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sai->pclk = devm_clk_get(&pdev->dev, "pclk");
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if (IS_ERR(sai->pclk)) {
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dev_err(&pdev->dev, "missing bus clock pclk\n");
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return PTR_ERR(sai->pclk);
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}
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}
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sai->clk_x8k = devm_clk_get(&pdev->dev, "x8k");
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if (IS_ERR(sai->clk_x8k)) {
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dev_err(&pdev->dev, "missing x8k parent clock\n");
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@ -92,16 +231,27 @@ static int stm32_sai_probe(struct platform_device *pdev)
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reset_control_deassert(rst);
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}
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ret = stm32_sai_sync_add_provider(pdev, sai);
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if (ret < 0)
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return ret;
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sai->set_sync = &stm32_sai_set_sync;
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sai->pdev = pdev;
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platform_set_drvdata(pdev, sai);
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return of_platform_populate(np, NULL, NULL, &pdev->dev);
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ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
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if (ret < 0)
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stm32_sai_sync_del_provider(np);
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return ret;
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}
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static int stm32_sai_remove(struct platform_device *pdev)
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{
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of_platform_depopulate(&pdev->dev);
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stm32_sai_sync_del_provider(pdev->dev.of_node);
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return 0;
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}
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|
|
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@ -16,9 +16,11 @@
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* details.
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*/
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#include <linux/bitfield.h>
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/******************** SAI Register Map **************************************/
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/* common register */
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/* Global configuration register */
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#define STM_SAI_GCR 0x00
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/* Sub-block A&B registers offsets, relative to A&B sub-block addresses */
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@ -37,12 +39,13 @@
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/******************** Bit definition for SAI_GCR register *******************/
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#define SAI_GCR_SYNCIN_SHIFT 0
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#define SAI_GCR_SYNCIN_WDTH 2
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#define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT)
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#define SAI_GCR_SYNCIN_SET(x) ((x) << SAI_GCR_SYNCIN_SHIFT)
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#define SAI_GCR_SYNCIN_MAX FIELD_GET(SAI_GCR_SYNCIN_MASK,\
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SAI_GCR_SYNCIN_MASK)
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#define SAI_GCR_SYNCOUT_SHIFT 4
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#define SAI_GCR_SYNCOUT_MASK GENMASK(5, SAI_GCR_SYNCOUT_SHIFT)
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#define SAI_GCR_SYNCOUT_SET(x) ((x) << SAI_GCR_SYNCOUT_SHIFT)
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/******************* Bit definition for SAI_XCR1 register *******************/
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#define SAI_XCR1_RX_TX_SHIFT 0
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|
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@ -231,6 +234,12 @@
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#define STM_SAI_IS_F4(ip) ((ip)->conf->version == SAI_STM32F4)
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#define STM_SAI_IS_H7(ip) ((ip)->conf->version == SAI_STM32H7)
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|
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enum stm32_sai_syncout {
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STM_SAI_SYNC_OUT_NONE,
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STM_SAI_SYNC_OUT_A,
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STM_SAI_SYNC_OUT_B,
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};
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|
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enum stm32_sai_version {
|
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SAI_STM32F4,
|
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SAI_STM32H7
|
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|
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@ -247,15 +256,22 @@ struct stm32_sai_conf {
|
|||
/**
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* struct stm32_sai_data - private data of SAI instance driver
|
||||
* @pdev: device data pointer
|
||||
* @base: common register bank virtual base address
|
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* @pclk: SAI bus clock
|
||||
* @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz
|
||||
* @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz
|
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* @version: SOC version
|
||||
* @irq: SAI interrupt line
|
||||
* @set_sync: pointer to synchro mode configuration callback
|
||||
*/
|
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struct stm32_sai_data {
|
||||
struct platform_device *pdev;
|
||||
void __iomem *base;
|
||||
struct clk *pclk;
|
||||
struct clk *clk_x8k;
|
||||
struct clk *clk_x11k;
|
||||
struct stm32_sai_conf *conf;
|
||||
int irq;
|
||||
int (*set_sync)(struct stm32_sai_data *sai,
|
||||
struct device_node *np_provider, int synco, int synci);
|
||||
};
|
||||
|
|
|
|||
|
|
@ -55,6 +55,12 @@
|
|||
#define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID)
|
||||
#define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B")
|
||||
|
||||
#define SAI_SYNC_NONE 0x0
|
||||
#define SAI_SYNC_INTERNAL 0x1
|
||||
#define SAI_SYNC_EXTERNAL 0x2
|
||||
|
||||
#define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
|
||||
|
||||
/**
|
||||
* struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
|
||||
* @pdev: device data pointer
|
||||
|
|
@ -65,6 +71,7 @@
|
|||
* @cpu_dai: DAI runtime data pointer
|
||||
* @substream: PCM substream data pointer
|
||||
* @pdata: SAI block parent data pointer
|
||||
* @np_sync_provider: synchronization provider node
|
||||
* @sai_ck: kernel clock feeding the SAI clock generator
|
||||
* @phys_addr: SAI registers physical base address
|
||||
* @mclk_rate: SAI block master clock frequency (Hz). set at init
|
||||
|
|
@ -73,6 +80,8 @@
|
|||
* @master: SAI block mode flag. (true=master, false=slave) set at init
|
||||
* @fmt: SAI block format. relevant only for custom protocols. set at init
|
||||
* @sync: SAI block synchronization mode. (none, internal or external)
|
||||
* @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
|
||||
* @synci: SAI block ext sync source (client setting). (SAI sync provider index)
|
||||
* @fs_length: frame synchronization length. depends on protocol settings
|
||||
* @slots: rx or tx slot number
|
||||
* @slot_width: rx or tx slot width in bits
|
||||
|
|
@ -88,6 +97,7 @@ struct stm32_sai_sub_data {
|
|||
struct snd_soc_dai *cpu_dai;
|
||||
struct snd_pcm_substream *substream;
|
||||
struct stm32_sai_data *pdata;
|
||||
struct device_node *np_sync_provider;
|
||||
struct clk *sai_ck;
|
||||
dma_addr_t phys_addr;
|
||||
unsigned int mclk_rate;
|
||||
|
|
@ -96,6 +106,8 @@ struct stm32_sai_sub_data {
|
|||
bool master;
|
||||
int fmt;
|
||||
int sync;
|
||||
int synco;
|
||||
int synci;
|
||||
int fs_length;
|
||||
int slots;
|
||||
int slot_width;
|
||||
|
|
@ -308,12 +320,15 @@ static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
|
|||
static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
|
||||
{
|
||||
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
|
||||
int cr1 = 0, frcr = 0;
|
||||
int cr1_mask = 0, frcr_mask = 0;
|
||||
int cr1, frcr = 0;
|
||||
int cr1_mask, frcr_mask = 0;
|
||||
int ret;
|
||||
|
||||
dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
|
||||
|
||||
cr1_mask = SAI_XCR1_PRTCFG_MASK;
|
||||
cr1 = SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
|
||||
|
||||
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
||||
/* SCK active high for all protocols */
|
||||
case SND_SOC_DAIFMT_I2S:
|
||||
|
|
@ -340,7 +355,7 @@ static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
cr1_mask |= SAI_XCR1_PRTCFG_MASK | SAI_XCR1_CKSTR;
|
||||
cr1_mask |= SAI_XCR1_CKSTR;
|
||||
frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
|
||||
SAI_XFRCR_FSDEF;
|
||||
|
||||
|
|
@ -384,6 +399,14 @@ static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
|
|||
fmt & SND_SOC_DAIFMT_MASTER_MASK);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Set slave mode if sub-block is synchronized with another SAI */
|
||||
if (sai->sync) {
|
||||
dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n");
|
||||
cr1 |= SAI_XCR1_SLAVE;
|
||||
sai->master = false;
|
||||
}
|
||||
|
||||
cr1_mask |= SAI_XCR1_SLAVE;
|
||||
|
||||
/* do not generate master by default */
|
||||
|
|
@ -416,8 +439,6 @@ static int stm32_sai_startup(struct snd_pcm_substream *substream,
|
|||
}
|
||||
|
||||
/* Enable ITs */
|
||||
regmap_update_bits(sai->regmap, STM_SAI_SR_REGX,
|
||||
SAI_XSR_MASK, (unsigned int)~SAI_XSR_MASK);
|
||||
|
||||
regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX,
|
||||
SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
|
||||
|
|
@ -458,26 +479,21 @@ static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
|
|||
SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF));
|
||||
|
||||
/* Mode, data format and channel config */
|
||||
cr1 = SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
|
||||
cr1_mask = SAI_XCR1_DS_MASK;
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S8:
|
||||
cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_8);
|
||||
cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_16);
|
||||
cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S32_LE:
|
||||
cr1 |= SAI_XCR1_DS_SET(SAI_DATASIZE_32);
|
||||
cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);
|
||||
break;
|
||||
default:
|
||||
dev_err(cpu_dai->dev, "Data format not supported");
|
||||
return -EINVAL;
|
||||
}
|
||||
cr1_mask = SAI_XCR1_DS_MASK | SAI_XCR1_PRTCFG_MASK;
|
||||
|
||||
cr1_mask |= SAI_XCR1_RX_TX;
|
||||
if (STM_SAI_IS_CAPTURE(sai))
|
||||
cr1 |= SAI_XCR1_RX_TX;
|
||||
|
||||
cr1_mask |= SAI_XCR1_MONO;
|
||||
if ((sai->slots == 2) && (params_channels(params) == 1))
|
||||
|
|
@ -695,6 +711,9 @@ static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
|
|||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
|
||||
|
||||
regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
|
||||
SAI_XIMR_MASK, 0);
|
||||
|
||||
regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
|
||||
SAI_XCR1_SAIEN,
|
||||
(unsigned int)~SAI_XCR1_SAIEN);
|
||||
|
|
@ -729,6 +748,7 @@ static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
|
|||
static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
|
||||
{
|
||||
struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
|
||||
int cr1 = 0, cr1_mask;
|
||||
|
||||
sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
|
||||
/*
|
||||
|
|
@ -745,7 +765,21 @@ static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
|
|||
else
|
||||
snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
|
||||
|
||||
return 0;
|
||||
cr1_mask = SAI_XCR1_RX_TX;
|
||||
if (STM_SAI_IS_CAPTURE(sai))
|
||||
cr1 |= SAI_XCR1_RX_TX;
|
||||
|
||||
/* Configure synchronization */
|
||||
if (sai->sync == SAI_SYNC_EXTERNAL) {
|
||||
/* Configure synchro client and provider */
|
||||
sai->pdata->set_sync(sai->pdata, sai->np_sync_provider,
|
||||
sai->synco, sai->synci);
|
||||
}
|
||||
|
||||
cr1_mask |= SAI_XCR1_SYNCEN_MASK;
|
||||
cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);
|
||||
|
||||
return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
|
||||
}
|
||||
|
||||
static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
|
||||
|
|
@ -831,6 +865,8 @@ static int stm32_sai_sub_parse_of(struct platform_device *pdev,
|
|||
struct device_node *np = pdev->dev.of_node;
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
struct of_phandle_args args;
|
||||
int ret;
|
||||
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
|
|
@ -864,6 +900,69 @@ static int stm32_sai_sub_parse_of(struct platform_device *pdev,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Get synchronization property */
|
||||
args.np = NULL;
|
||||
ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args);
|
||||
if (ret < 0 && ret != -ENOENT) {
|
||||
dev_err(&pdev->dev, "Failed to get st,sync property\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
sai->sync = SAI_SYNC_NONE;
|
||||
if (args.np) {
|
||||
if (args.np == np) {
|
||||
dev_err(&pdev->dev, "%s sync own reference\n",
|
||||
np->name);
|
||||
of_node_put(args.np);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sai->np_sync_provider = of_get_parent(args.np);
|
||||
if (!sai->np_sync_provider) {
|
||||
dev_err(&pdev->dev, "%s parent node not found\n",
|
||||
np->name);
|
||||
of_node_put(args.np);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
sai->sync = SAI_SYNC_INTERNAL;
|
||||
if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) {
|
||||
if (!STM_SAI_HAS_EXT_SYNC(sai)) {
|
||||
dev_err(&pdev->dev,
|
||||
"External synchro not supported\n");
|
||||
of_node_put(args.np);
|
||||
return -EINVAL;
|
||||
}
|
||||
sai->sync = SAI_SYNC_EXTERNAL;
|
||||
|
||||
sai->synci = args.args[0];
|
||||
if (sai->synci < 1 ||
|
||||
(sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) {
|
||||
dev_err(&pdev->dev, "Wrong SAI index\n");
|
||||
of_node_put(args.np);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (of_property_match_string(args.np, "compatible",
|
||||
"st,stm32-sai-sub-a") >= 0)
|
||||
sai->synco = STM_SAI_SYNC_OUT_A;
|
||||
|
||||
if (of_property_match_string(args.np, "compatible",
|
||||
"st,stm32-sai-sub-b") >= 0)
|
||||
sai->synco = STM_SAI_SYNC_OUT_B;
|
||||
|
||||
if (!sai->synco) {
|
||||
dev_err(&pdev->dev, "Unknown SAI sub-block\n");
|
||||
of_node_put(args.np);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
dev_dbg(&pdev->dev, "%s synchronized with %s\n",
|
||||
pdev->name, args.np->full_name);
|
||||
}
|
||||
|
||||
of_node_put(args.np);
|
||||
sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
|
||||
if (IS_ERR(sai->sai_ck)) {
|
||||
dev_err(&pdev->dev, "Missing kernel clock sai_ck\n");
|
||||
|
|
|
|||
|
|
@ -392,6 +392,12 @@ static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
|
|||
{
|
||||
int ret;
|
||||
|
||||
spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
|
||||
if (IS_ERR(spdifrx->ctrl_chan)) {
|
||||
dev_err(dev, "dma_request_slave_channel failed\n");
|
||||
return PTR_ERR(spdifrx->ctrl_chan);
|
||||
}
|
||||
|
||||
spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
|
||||
GFP_KERNEL);
|
||||
if (!spdifrx->dmab)
|
||||
|
|
@ -406,12 +412,6 @@ static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
|
|||
return ret;
|
||||
}
|
||||
|
||||
spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
|
||||
if (!spdifrx->ctrl_chan) {
|
||||
dev_err(dev, "dma_request_slave_channel failed\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
|
||||
spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
|
||||
STM32_SPDIFRX_CSR);
|
||||
|
|
@ -423,7 +423,6 @@ static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
|
|||
&spdifrx->slave_config);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
|
||||
dma_release_channel(spdifrx->ctrl_chan);
|
||||
spdifrx->ctrl_chan = NULL;
|
||||
}
|
||||
|
||||
|
|
@ -750,17 +749,21 @@ static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
|
|||
switch (data_size) {
|
||||
case 16:
|
||||
fmt = SPDIFRX_DRFMT_PACKED;
|
||||
spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
||||
break;
|
||||
case 32:
|
||||
fmt = SPDIFRX_DRFMT_LEFT;
|
||||
spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
break;
|
||||
default:
|
||||
dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set buswidth to 4 bytes for all data formats.
|
||||
* Packed format: transfer 2 x 2 bytes samples
|
||||
* Left format: transfer 1 x 3 bytes samples + 1 dummy byte
|
||||
*/
|
||||
spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
|
||||
|
||||
return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
|
||||
|
|
@ -958,7 +961,7 @@ static int stm32_spdifrx_probe(struct platform_device *pdev)
|
|||
return 0;
|
||||
|
||||
error:
|
||||
if (spdifrx->ctrl_chan)
|
||||
if (!IS_ERR(spdifrx->ctrl_chan))
|
||||
dma_release_channel(spdifrx->ctrl_chan);
|
||||
if (spdifrx->dmab)
|
||||
snd_dma_free_pages(spdifrx->dmab);
|
||||
|
|
|
|||
|
|
@ -346,11 +346,6 @@ static int sun4i_codec_prepare_capture(struct snd_pcm_substream *substream,
|
|||
0x3 << 8,
|
||||
0x1 << 8);
|
||||
|
||||
/* Fill most significant bits with valid data MSB */
|
||||
regmap_field_update_bits(scodec->reg_adc_fifoc,
|
||||
BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE),
|
||||
BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -490,6 +485,30 @@ static int sun4i_codec_hw_params_capture(struct sun4i_codec *scodec,
|
|||
BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN),
|
||||
0);
|
||||
|
||||
/* Set the number of sample bits to either 16 or 24 bits */
|
||||
if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
|
||||
regmap_field_update_bits(scodec->reg_adc_fifoc,
|
||||
BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS),
|
||||
BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS));
|
||||
|
||||
regmap_field_update_bits(scodec->reg_adc_fifoc,
|
||||
BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE),
|
||||
0);
|
||||
|
||||
scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
} else {
|
||||
regmap_field_update_bits(scodec->reg_adc_fifoc,
|
||||
BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS),
|
||||
0);
|
||||
|
||||
/* Fill most significant bits with valid data MSB */
|
||||
regmap_field_update_bits(scodec->reg_adc_fifoc,
|
||||
BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE),
|
||||
BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
|
||||
|
||||
scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -198,9 +198,20 @@ static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
|
|||
regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
|
||||
BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV),
|
||||
value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
|
||||
|
||||
/*
|
||||
* It appears that the DAI and the codec don't share the same
|
||||
* polarity for the LRCK signal when they mean 'normal' and
|
||||
* 'inverted' in the datasheet.
|
||||
*
|
||||
* Since the DAI here is our regular i2s driver that have been
|
||||
* tested with way more codecs than just this one, it means
|
||||
* that the codec probably gets it backward, and we have to
|
||||
* invert the value here.
|
||||
*/
|
||||
regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
|
||||
BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV),
|
||||
value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
|
||||
!value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
|
||||
|
||||
/* DAI format */
|
||||
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue