ASoC: Implement WM8994 OPCLK support
The WM8994 can output a clock derived from its internal SYSCLK, called OPCLK. The rate can be selected as a sysclk, with a division from the SYSCLK rate specified (multiplied by 10 since a division of 5.5 is supported) and the clock can be disabled by specifying a divisor of zero. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
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@ -2492,6 +2492,7 @@ static const struct snd_kcontrol_new aif3adc_mux =
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static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
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SND_SOC_DAPM_INPUT("DMIC1DAT"),
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SND_SOC_DAPM_INPUT("DMIC2DAT"),
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SND_SOC_DAPM_INPUT("Clock"),
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SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
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SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
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@ -2966,11 +2967,14 @@ static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
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return 0;
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}
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static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
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static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
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int i;
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switch (dai->id) {
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case 1:
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@ -3008,6 +3012,25 @@ static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
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dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
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break;
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case WM8994_SYSCLK_OPCLK:
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/* Special case - a division (times 10) is given and
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* no effect on main clocking.
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*/
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if (freq) {
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for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
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if (opclk_divs[i] == freq)
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break;
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if (i == ARRAY_SIZE(opclk_divs))
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return -EINVAL;
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snd_soc_update_bits(codec, WM8994_CLOCKING_2,
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WM8994_OPCLK_DIV_MASK, i);
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snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
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WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
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} else {
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snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
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WM8994_OPCLK_ENA, 0);
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}
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default:
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return -EINVAL;
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}
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@ -20,6 +20,9 @@ extern struct snd_soc_dai wm8994_dai[];
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#define WM8994_SYSCLK_FLL1 3
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#define WM8994_SYSCLK_FLL2 4
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/* OPCLK is also configured with set_dai_sysclk, specify division*10 as rate. */
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#define WM8994_SYSCLK_OPCLK 5
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#define WM8994_FLL1 1
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#define WM8994_FLL2 2
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