Merge remote-tracking branches 'spi/topic/octeon', 'spi/topic/pic32-sqi', 'spi/topic/pxa2xx' and 'spi/topic/qup' into spi-next
Mark Brown
commit
66b5a337d0
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@ -648,6 +648,13 @@ config SPI_TEGRA20_SLINK
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help
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SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface.
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config SPI_THUNDERX
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tristate "Cavium ThunderX SPI controller"
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depends on PCI && 64BIT && (ARM64 || COMPILE_TEST)
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help
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SPI host driver for the hardware found on Cavium ThunderX
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SOCs.
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config SPI_TOPCLIFF_PCH
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tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI"
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depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
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@ -93,6 +93,8 @@ obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
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obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
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obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o
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obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
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spi-thunderx-objs := spi-cavium.o spi-cavium-thunderx.o
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obj-$(CONFIG_SPI_THUNDERX) += spi-thunderx.o
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obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
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obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
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obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o
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@ -0,0 +1,120 @@
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/*
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* Cavium ThunderX SPI driver.
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*
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* Copyright (C) 2016 Cavium Inc.
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* Authors: Jan Glauber <jglauber@cavium.com>
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/spi/spi.h>
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#include "spi-cavium.h"
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#define DRV_NAME "spi-thunderx"
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#define SYS_FREQ_DEFAULT 700000000 /* 700 Mhz */
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static int thunderx_spi_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct device *dev = &pdev->dev;
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struct spi_master *master;
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struct octeon_spi *p;
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int ret;
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master = spi_alloc_master(dev, sizeof(struct octeon_spi));
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if (!master)
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return -ENOMEM;
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p = spi_master_get_devdata(master);
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ret = pcim_enable_device(pdev);
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if (ret)
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goto error;
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ret = pci_request_regions(pdev, DRV_NAME);
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if (ret)
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goto error;
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p->register_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));
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if (!p->register_base) {
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ret = -EINVAL;
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goto error;
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}
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p->regs.config = 0x1000;
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p->regs.status = 0x1008;
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p->regs.tx = 0x1010;
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p->regs.data = 0x1080;
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p->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(p->clk)) {
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ret = PTR_ERR(p->clk);
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goto error;
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}
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ret = clk_prepare_enable(p->clk);
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if (ret)
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goto error;
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p->sys_freq = clk_get_rate(p->clk);
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if (!p->sys_freq)
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p->sys_freq = SYS_FREQ_DEFAULT;
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dev_info(dev, "Set system clock to %u\n", p->sys_freq);
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master->num_chipselect = 4;
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master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
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SPI_LSB_FIRST | SPI_3WIRE;
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master->transfer_one_message = octeon_spi_transfer_one_message;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
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master->dev.of_node = pdev->dev.of_node;
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pci_set_drvdata(pdev, master);
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ret = devm_spi_register_master(dev, master);
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if (ret)
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goto error;
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return 0;
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error:
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clk_disable_unprepare(p->clk);
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spi_master_put(master);
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return ret;
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}
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static void thunderx_spi_remove(struct pci_dev *pdev)
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{
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struct spi_master *master = pci_get_drvdata(pdev);
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struct octeon_spi *p;
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p = spi_master_get_devdata(master);
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if (!p)
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return;
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clk_disable_unprepare(p->clk);
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/* Put everything in a known state. */
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writeq(0, p->register_base + OCTEON_SPI_CFG(p));
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}
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static const struct pci_device_id thunderx_spi_pci_id_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xa00b) },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, thunderx_spi_pci_id_table);
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static struct pci_driver thunderx_spi_driver = {
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.name = DRV_NAME,
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.id_table = thunderx_spi_pci_id_table,
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.probe = thunderx_spi_probe,
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.remove = thunderx_spi_remove,
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};
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module_pci_driver(thunderx_spi_driver);
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MODULE_DESCRIPTION("Cavium, Inc. ThunderX SPI bus driver");
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MODULE_AUTHOR("Jan Glauber");
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MODULE_LICENSE("GPL");
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@ -1,6 +1,8 @@
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#ifndef __SPI_CAVIUM_H
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#define __SPI_CAVIUM_H
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#include <linux/clk.h>
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#define OCTEON_SPI_MAX_BYTES 9
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#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
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@ -17,6 +19,7 @@ struct octeon_spi {
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u64 cs_enax;
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int sys_freq;
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struct octeon_spi_regs regs;
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struct clk *clk;
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};
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#define OCTEON_SPI_CFG(x) (x->regs.config)
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@ -253,15 +253,13 @@ static struct ring_desc *ring_desc_get(struct pic32_sqi *sqi)
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return NULL;
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rdesc = list_first_entry(&sqi->bd_list_free, struct ring_desc, list);
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list_del(&rdesc->list);
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list_add_tail(&rdesc->list, &sqi->bd_list_used);
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list_move_tail(&rdesc->list, &sqi->bd_list_used);
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return rdesc;
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}
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static void ring_desc_put(struct pic32_sqi *sqi, struct ring_desc *rdesc)
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{
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list_del(&rdesc->list);
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list_add(&rdesc->list, &sqi->bd_list_free);
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list_move(&rdesc->list, &sqi->bd_list_free);
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}
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static int pic32_sqi_one_transfer(struct pic32_sqi *sqi,
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@ -23,7 +23,7 @@
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static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
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bool error)
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{
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struct spi_message *msg = drv_data->cur_msg;
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struct spi_message *msg = drv_data->master->cur_msg;
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/*
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* It is possible that one CPU is handling ROR interrupt and other
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@ -76,7 +76,8 @@ static struct dma_async_tx_descriptor *
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pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
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enum dma_transfer_direction dir)
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{
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struct chip_data *chip = drv_data->cur_chip;
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struct chip_data *chip =
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spi_get_ctldata(drv_data->master->cur_msg->spi);
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struct spi_transfer *xfer = drv_data->cur_transfer;
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enum dma_slave_buswidth width;
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struct dma_slave_config cfg;
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@ -146,7 +147,7 @@ irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
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int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst)
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{
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struct dma_async_tx_descriptor *tx_desc, *rx_desc;
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int err = 0;
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int err;
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tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV);
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if (!tx_desc) {
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@ -28,6 +28,7 @@
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#include <linux/spi/spi.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/gpio/consumer.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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@ -62,6 +63,13 @@ MODULE_ALIAS("platform:pxa2xx-spi");
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| QUARK_X1000_SSCR1_TFT \
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| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
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#define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
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| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
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| SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
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| SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
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| CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
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| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
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#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
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#define LPSS_CS_CONTROL_SW_MODE BIT(0)
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#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
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@ -175,6 +183,8 @@ static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
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switch (drv_data->ssp_type) {
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case QUARK_X1000_SSP:
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return QUARK_X1000_SSCR1_CHANGE_MASK;
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case CE4100_SSP:
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return CE4100_SSCR1_CHANGE_MASK;
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default:
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return SSCR1_CHANGE_MASK;
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}
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@ -186,6 +196,8 @@ pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
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switch (drv_data->ssp_type) {
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case QUARK_X1000_SSP:
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return RX_THRESH_QUARK_X1000_DFLT;
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case CE4100_SSP:
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return RX_THRESH_CE4100_DFLT;
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default:
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return RX_THRESH_DFLT;
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}
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@ -199,6 +211,9 @@ static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
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case QUARK_X1000_SSP:
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mask = QUARK_X1000_SSSR_TFL_MASK;
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break;
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case CE4100_SSP:
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mask = CE4100_SSSR_TFL_MASK;
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break;
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default:
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mask = SSSR_TFL_MASK;
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break;
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@ -216,6 +231,9 @@ static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
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case QUARK_X1000_SSP:
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mask = QUARK_X1000_SSCR1_RFT;
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break;
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case CE4100_SSP:
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mask = CE4100_SSCR1_RFT;
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break;
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default:
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mask = SSCR1_RFT;
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break;
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@ -230,6 +248,9 @@ static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
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case QUARK_X1000_SSP:
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*sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
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break;
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case CE4100_SSP:
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*sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
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break;
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default:
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*sccr1_reg |= SSCR1_RxTresh(threshold);
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break;
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@ -316,7 +337,7 @@ static void lpss_ssp_select_cs(struct driver_data *drv_data,
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value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
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cs = drv_data->cur_msg->spi->chip_select;
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cs = drv_data->master->cur_msg->spi->chip_select;
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cs <<= config->cs_sel_shift;
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if (cs != (value & config->cs_sel_mask)) {
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/*
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@ -355,10 +376,11 @@ static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
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static void cs_assert(struct driver_data *drv_data)
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{
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struct chip_data *chip = drv_data->cur_chip;
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struct chip_data *chip =
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spi_get_ctldata(drv_data->master->cur_msg->spi);
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if (drv_data->ssp_type == CE4100_SSP) {
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pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
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pxa2xx_spi_write(drv_data, SSSR, chip->frm);
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return;
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}
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@ -378,7 +400,8 @@ static void cs_assert(struct driver_data *drv_data)
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static void cs_deassert(struct driver_data *drv_data)
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{
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struct chip_data *chip = drv_data->cur_chip;
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struct chip_data *chip =
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spi_get_ctldata(drv_data->master->cur_msg->spi);
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if (drv_data->ssp_type == CE4100_SSP)
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return;
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@ -508,7 +531,7 @@ static int u32_reader(struct driver_data *drv_data)
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void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
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{
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struct spi_message *msg = drv_data->cur_msg;
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struct spi_message *msg = drv_data->master->cur_msg;
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struct spi_transfer *trans = drv_data->cur_transfer;
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/* Move to next transfer */
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@ -529,8 +552,7 @@ static void giveback(struct driver_data *drv_data)
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struct spi_message *msg;
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unsigned long timeout;
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msg = drv_data->cur_msg;
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drv_data->cur_msg = NULL;
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msg = drv_data->master->cur_msg;
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drv_data->cur_transfer = NULL;
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last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
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@ -575,13 +597,13 @@ static void giveback(struct driver_data *drv_data)
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cs_deassert(drv_data);
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}
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drv_data->cur_chip = NULL;
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spi_finalize_current_message(drv_data->master);
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}
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static void reset_sccr1(struct driver_data *drv_data)
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{
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struct chip_data *chip = drv_data->cur_chip;
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struct chip_data *chip =
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spi_get_ctldata(drv_data->master->cur_msg->spi);
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u32 sccr1_reg;
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sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
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@ -589,6 +611,9 @@ static void reset_sccr1(struct driver_data *drv_data)
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case QUARK_X1000_SSP:
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sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
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break;
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case CE4100_SSP:
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sccr1_reg &= ~CE4100_SSCR1_RFT;
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break;
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default:
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sccr1_reg &= ~SSCR1_RFT;
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break;
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@ -610,7 +635,7 @@ static void int_error_stop(struct driver_data *drv_data, const char* msg)
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dev_err(&drv_data->pdev->dev, "%s\n", msg);
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drv_data->cur_msg->state = ERROR_STATE;
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drv_data->master->cur_msg->state = ERROR_STATE;
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tasklet_schedule(&drv_data->pump_transfers);
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}
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@ -623,7 +648,7 @@ static void int_transfer_complete(struct driver_data *drv_data)
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pxa2xx_spi_write(drv_data, SSTO, 0);
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/* Update total byte transferred return count actual bytes read */
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drv_data->cur_msg->actual_length += drv_data->len -
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drv_data->master->cur_msg->actual_length += drv_data->len -
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(drv_data->rx_end - drv_data->rx);
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/* Transfer delays and chip select release are
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||||
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@ -631,7 +656,7 @@ static void int_transfer_complete(struct driver_data *drv_data)
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*/
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||||
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/* Move to next transfer */
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drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
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drv_data->master->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
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||||
|
||||
/* Schedule transfer tasklet */
|
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tasklet_schedule(&drv_data->pump_transfers);
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||||
|
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@ -746,7 +771,7 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
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if (!(status & mask))
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return IRQ_NONE;
|
||||
|
||||
if (!drv_data->cur_msg) {
|
||||
if (!drv_data->master->cur_msg) {
|
||||
|
||||
pxa2xx_spi_write(drv_data, SSCR0,
|
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pxa2xx_spi_read(drv_data, SSCR0)
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||||
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|
@ -905,7 +930,8 @@ static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
|
|||
static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
|
||||
int rate)
|
||||
{
|
||||
struct chip_data *chip = drv_data->cur_chip;
|
||||
struct chip_data *chip =
|
||||
spi_get_ctldata(drv_data->master->cur_msg->spi);
|
||||
unsigned int clk_div;
|
||||
|
||||
switch (drv_data->ssp_type) {
|
||||
|
|
@ -934,25 +960,23 @@ static void pump_transfers(unsigned long data)
|
|||
{
|
||||
struct driver_data *drv_data = (struct driver_data *)data;
|
||||
struct spi_master *master = drv_data->master;
|
||||
struct spi_message *message = NULL;
|
||||
struct spi_transfer *transfer = NULL;
|
||||
struct spi_transfer *previous = NULL;
|
||||
struct chip_data *chip = NULL;
|
||||
u32 clk_div = 0;
|
||||
u8 bits = 0;
|
||||
u32 speed = 0;
|
||||
struct spi_message *message = master->cur_msg;
|
||||
struct chip_data *chip = spi_get_ctldata(message->spi);
|
||||
u32 dma_thresh = chip->dma_threshold;
|
||||
u32 dma_burst = chip->dma_burst_size;
|
||||
u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
|
||||
struct spi_transfer *transfer;
|
||||
struct spi_transfer *previous;
|
||||
u32 clk_div;
|
||||
u8 bits;
|
||||
u32 speed;
|
||||
u32 cr0;
|
||||
u32 cr1;
|
||||
u32 dma_thresh = drv_data->cur_chip->dma_threshold;
|
||||
u32 dma_burst = drv_data->cur_chip->dma_burst_size;
|
||||
u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
|
||||
int err;
|
||||
int dma_mapped;
|
||||
|
||||
/* Get current state information */
|
||||
message = drv_data->cur_msg;
|
||||
transfer = drv_data->cur_transfer;
|
||||
chip = drv_data->cur_chip;
|
||||
|
||||
/* Handle for abort */
|
||||
if (message->state == ERROR_STATE) {
|
||||
|
|
@ -1146,17 +1170,12 @@ static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
|
|||
{
|
||||
struct driver_data *drv_data = spi_master_get_devdata(master);
|
||||
|
||||
drv_data->cur_msg = msg;
|
||||
/* Initial message state*/
|
||||
drv_data->cur_msg->state = START_STATE;
|
||||
drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
|
||||
msg->state = START_STATE;
|
||||
drv_data->cur_transfer = list_entry(msg->transfers.next,
|
||||
struct spi_transfer,
|
||||
transfer_list);
|
||||
|
||||
/* prepare to setup the SSP, in pump_transfers, using the per
|
||||
* chip configuration */
|
||||
drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
|
||||
|
||||
/* Mark as busy and launch transfers */
|
||||
tasklet_schedule(&drv_data->pump_transfers);
|
||||
return 0;
|
||||
|
|
@ -1176,9 +1195,26 @@ static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
|
|||
static int setup_cs(struct spi_device *spi, struct chip_data *chip,
|
||||
struct pxa2xx_spi_chip *chip_info)
|
||||
{
|
||||
struct driver_data *drv_data = spi_master_get_devdata(spi->master);
|
||||
int err = 0;
|
||||
|
||||
if (chip == NULL || chip_info == NULL)
|
||||
if (chip == NULL)
|
||||
return 0;
|
||||
|
||||
if (drv_data->cs_gpiods) {
|
||||
struct gpio_desc *gpiod;
|
||||
|
||||
gpiod = drv_data->cs_gpiods[spi->chip_select];
|
||||
if (gpiod) {
|
||||
chip->gpio_cs = desc_to_gpio(gpiod);
|
||||
chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
|
||||
gpiod_set_value(gpiod, chip->gpio_cs_inverted);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (chip_info == NULL)
|
||||
return 0;
|
||||
|
||||
/* NOTE: setup() can be called multiple times, possibly with
|
||||
|
|
@ -1213,7 +1249,7 @@ static int setup_cs(struct spi_device *spi, struct chip_data *chip,
|
|||
|
||||
static int setup(struct spi_device *spi)
|
||||
{
|
||||
struct pxa2xx_spi_chip *chip_info = NULL;
|
||||
struct pxa2xx_spi_chip *chip_info;
|
||||
struct chip_data *chip;
|
||||
const struct lpss_config *config;
|
||||
struct driver_data *drv_data = spi_master_get_devdata(spi->master);
|
||||
|
|
@ -1225,6 +1261,11 @@ static int setup(struct spi_device *spi)
|
|||
tx_hi_thres = 0;
|
||||
rx_thres = RX_THRESH_QUARK_X1000_DFLT;
|
||||
break;
|
||||
case CE4100_SSP:
|
||||
tx_thres = TX_THRESH_CE4100_DFLT;
|
||||
tx_hi_thres = 0;
|
||||
rx_thres = RX_THRESH_CE4100_DFLT;
|
||||
break;
|
||||
case LPSS_LPT_SSP:
|
||||
case LPSS_BYT_SSP:
|
||||
case LPSS_BSW_SSP:
|
||||
|
|
@ -1309,6 +1350,10 @@ static int setup(struct spi_device *spi)
|
|||
| (QUARK_X1000_SSCR1_TxTresh(tx_thres)
|
||||
& QUARK_X1000_SSCR1_TFT);
|
||||
break;
|
||||
case CE4100_SSP:
|
||||
chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
|
||||
(CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
|
||||
break;
|
||||
default:
|
||||
chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
|
||||
(SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
|
||||
|
|
@ -1352,7 +1397,8 @@ static void cleanup(struct spi_device *spi)
|
|||
if (!chip)
|
||||
return;
|
||||
|
||||
if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
|
||||
if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
|
||||
gpio_is_valid(chip->gpio_cs))
|
||||
gpio_free(chip->gpio_cs);
|
||||
|
||||
kfree(chip);
|
||||
|
|
@ -1530,7 +1576,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
|
|||
struct driver_data *drv_data;
|
||||
struct ssp_device *ssp;
|
||||
const struct lpss_config *config;
|
||||
int status;
|
||||
int status, count;
|
||||
u32 tmp;
|
||||
|
||||
platform_info = dev_get_platdata(dev);
|
||||
|
|
@ -1630,15 +1676,20 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
|
|||
pxa2xx_spi_write(drv_data, SSCR0, 0);
|
||||
switch (drv_data->ssp_type) {
|
||||
case QUARK_X1000_SSP:
|
||||
tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
|
||||
| QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
|
||||
tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
|
||||
QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
|
||||
pxa2xx_spi_write(drv_data, SSCR1, tmp);
|
||||
|
||||
/* using the Motorola SPI protocol and use 8 bit frame */
|
||||
pxa2xx_spi_write(drv_data, SSCR0,
|
||||
QUARK_X1000_SSCR0_Motorola
|
||||
| QUARK_X1000_SSCR0_DataSize(8));
|
||||
tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
|
||||
pxa2xx_spi_write(drv_data, SSCR0, tmp);
|
||||
break;
|
||||
case CE4100_SSP:
|
||||
tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
|
||||
CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
|
||||
pxa2xx_spi_write(drv_data, SSCR1, tmp);
|
||||
tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
|
||||
pxa2xx_spi_write(drv_data, SSCR0, tmp);
|
||||
default:
|
||||
tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
|
||||
SSCR1_TxTresh(TX_THRESH_DFLT);
|
||||
|
|
@ -1669,6 +1720,39 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
|
|||
}
|
||||
master->num_chipselect = platform_info->num_chipselect;
|
||||
|
||||
count = gpiod_count(&pdev->dev, "cs");
|
||||
if (count > 0) {
|
||||
int i;
|
||||
|
||||
master->num_chipselect = max_t(int, count,
|
||||
master->num_chipselect);
|
||||
|
||||
drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
|
||||
master->num_chipselect, sizeof(struct gpio_desc *),
|
||||
GFP_KERNEL);
|
||||
if (!drv_data->cs_gpiods) {
|
||||
status = -ENOMEM;
|
||||
goto out_error_clock_enabled;
|
||||
}
|
||||
|
||||
for (i = 0; i < master->num_chipselect; i++) {
|
||||
struct gpio_desc *gpiod;
|
||||
|
||||
gpiod = devm_gpiod_get_index(dev, "cs", i,
|
||||
GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(gpiod)) {
|
||||
/* Means use native chip select */
|
||||
if (PTR_ERR(gpiod) == -ENOENT)
|
||||
continue;
|
||||
|
||||
status = (int)PTR_ERR(gpiod);
|
||||
goto out_error_clock_enabled;
|
||||
} else {
|
||||
drv_data->cs_gpiods[i] = gpiod;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
tasklet_init(&drv_data->pump_transfers, pump_transfers,
|
||||
(unsigned long)drv_data);
|
||||
|
||||
|
|
@ -1742,7 +1826,7 @@ static int pxa2xx_spi_suspend(struct device *dev)
|
|||
{
|
||||
struct driver_data *drv_data = dev_get_drvdata(dev);
|
||||
struct ssp_device *ssp = drv_data->ssp;
|
||||
int status = 0;
|
||||
int status;
|
||||
|
||||
status = spi_master_suspend(drv_data->master);
|
||||
if (status != 0)
|
||||
|
|
@ -1759,7 +1843,7 @@ static int pxa2xx_spi_resume(struct device *dev)
|
|||
{
|
||||
struct driver_data *drv_data = dev_get_drvdata(dev);
|
||||
struct ssp_device *ssp = drv_data->ssp;
|
||||
int status = 0;
|
||||
int status;
|
||||
|
||||
/* Enable the SSP clock */
|
||||
if (!pm_runtime_suspended(dev))
|
||||
|
|
|
|||
|
|
@ -53,9 +53,7 @@ struct driver_data {
|
|||
atomic_t dma_running;
|
||||
|
||||
/* Current message transfer state info */
|
||||
struct spi_message *cur_msg;
|
||||
struct spi_transfer *cur_transfer;
|
||||
struct chip_data *cur_chip;
|
||||
size_t len;
|
||||
void *tx;
|
||||
void *tx_end;
|
||||
|
|
@ -68,6 +66,9 @@ struct driver_data {
|
|||
void (*cs_control)(u32 command);
|
||||
|
||||
void __iomem *lpss_base;
|
||||
|
||||
/* GPIOs for chip selects */
|
||||
struct gpio_desc **cs_gpiods;
|
||||
};
|
||||
|
||||
struct chip_data {
|
||||
|
|
|
|||
|
|
@ -982,8 +982,10 @@ static int spi_qup_suspend(struct device *device)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
clk_disable_unprepare(controller->cclk);
|
||||
clk_disable_unprepare(controller->iclk);
|
||||
if (!pm_runtime_suspended(device)) {
|
||||
clk_disable_unprepare(controller->cclk);
|
||||
clk_disable_unprepare(controller->iclk);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -83,7 +83,6 @@
|
|||
#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
|
||||
#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
|
||||
|
||||
#ifdef CONFIG_ARCH_PXA
|
||||
#define RX_THRESH_DFLT 8
|
||||
#define TX_THRESH_DFLT 8
|
||||
|
||||
|
|
@ -95,19 +94,16 @@
|
|||
#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
|
||||
#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
|
||||
|
||||
#else
|
||||
#define RX_THRESH_CE4100_DFLT 2
|
||||
#define TX_THRESH_CE4100_DFLT 2
|
||||
|
||||
#define RX_THRESH_DFLT 2
|
||||
#define TX_THRESH_DFLT 2
|
||||
#define CE4100_SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */
|
||||
#define CE4100_SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */
|
||||
|
||||
#define SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */
|
||||
#define SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */
|
||||
|
||||
#define SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */
|
||||
#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
|
||||
#define SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */
|
||||
#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
|
||||
#endif
|
||||
#define CE4100_SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */
|
||||
#define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
|
||||
#define CE4100_SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */
|
||||
#define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
|
||||
|
||||
/* QUARK_X1000 SSCR0 bit definition */
|
||||
#define QUARK_X1000_SSCR0_DSS (0x1F) /* Data Size Select (mask) */
|
||||
|
|
|
|||
Loading…
Reference in New Issue