This adds support for offloading the FSI low level bitbanging to the
ColdFire coprocessor of the Aspeed SoCs. All the pre-requisites have already been merged, this is the final piece in the puzzle. This branch also pull gpio/ib-aspeed which is a topic branch already in gpio/for-next (and thus in next) whic contains pre-requisites. Finally, there's also a bug fix to the sbefifo driver for some inconsistent use of a mutex in the error handling code. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJbVqMzAAoJEHM62YSLdExe+aUP/12vNZdYfZLKdEuQRztjUtpO k1E/jNLnH97GvP6553zcebVrDl/xKzaYlxRrk3d8BovM4VlDv20QPWwc08IjXFPA +ikIBtWwAevXMuV69hpc253wOutYG7tdrrTKKc6o4rBAR+3DXMLBQ5bbb7SzEypB JpavulJvFwaxVb2UioQ6AaQ5dWdOjgYyXZicx9bNrTaj8FaY2rIohMXSqeXDqqhX hxQdRYo/YQWxxCTOSGdUQp9Yyuni1gP4NeHYMZGloFhjGZglo3oTL7aiCtxcFQAQ KcYY49ESlqIhjdFAFVa0WFStVMFSo7PmIMIFm9tS69av3TKTbZjbnQfjjOcfi05G 0hc4x/st3VJyQmQHhOlOwA/F4KBk0JZWtq3fOoyT297x1Nah+3iuO/8diLcqvkAy tXepEKj9cJ5igQ0Lvv0QQnwwmDkzMyat3U6GYA5ELwuMtUeifzp1HlXdKDEttSP3 QFG4CgUjG82RHKiFPGB+sEIaZ8CGQR0MsrlQFihI902PM8spw8LoQmGKReEP2qaF WYERVLZ3r3C0kAIX2+HLInm1YL3bpBFbGJj/LJwnylmOLucCcqd3PlfzykzMZ5hN +21c8NXs7rRiP1n20NwpXtGGfAV1BgvnkikZ18zbv3uDD66PG2twklsCrEv4sedZ RzQTFdfwqB83g+ZKgiLi =C4C6 -----END PGP SIGNATURE----- Merge tag 'fsi-updates-2018-07-24' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/linux-fsi into char-misc-testing Ben writes: This adds support for offloading the FSI low level bitbanging to the ColdFire coprocessor of the Aspeed SoCs. All the pre-requisites have already been merged, this is the final piece in the puzzle. This branch also pull gpio/ib-aspeed which is a topic branch already in gpio/for-next (and thus in next) whic contains pre-requisites. Finally, there's also a bug fix to the sbefifo driver for some inconsistent use of a mutex in the error handling code.hifive-unleashed-5.1
Greg Kroah-Hartman
commit
670d198b61
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@ -0,0 +1,36 @@
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Device-tree bindings for ColdFire offloaded gpio-based FSI master driver
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------------------------------------------------------------------------
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Required properties:
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- compatible =
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"aspeed,ast2400-cf-fsi-master" for an AST2400 based system
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or
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"aspeed,ast2500-cf-fsi-master" for an AST2500 based system
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- clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
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- data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
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- enable-gpios = <gpio-descriptor>; : GPIO for enable signal
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- trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
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- mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
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functions (eg, external FSI masters)
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- memory-region = <phandle>; : Reference to the reserved memory for
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the ColdFire. Must be 2M aligned on
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AST2400 and 1M aligned on AST2500
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- aspeed,sram = <phandle>; : Reference to the SRAM node.
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- aspeed,cvic = <phandle>; : Reference to the CVIC node.
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Examples:
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fsi-master {
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compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master";
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clock-gpios = <&gpio 0>;
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data-gpios = <&gpio 1>;
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enable-gpios = <&gpio 2>;
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trans-gpios = <&gpio 3>;
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mux-gpios = <&gpio 4>;
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memory-region = <&coldfire_memory>;
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aspeed,sram = <&sram>;
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aspeed,cvic = <&cvic>;
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}
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@ -83,6 +83,10 @@ addresses and sizes in the slave address space:
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#address-cells = <1>;
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#size-cells = <1>;
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Optionally, a slave can provide a global unique chip ID which is used to
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identify the physical location of the chip in a system specific way
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chip-id = <0>;
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FSI engines (devices)
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---------------------
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@ -125,6 +129,7 @@ device tree if no extra platform information is required.
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reg = <0 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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chip-id = <0>;
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/* FSI engine at 0xc00, using a single page. In this example,
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* it's an I2C master controller, so subnodes describe the
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@ -27,6 +27,15 @@ config FSI_MASTER_HUB
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allow chaining of FSI links to an arbitrary depth. This allows for
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a high target device fanout.
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config FSI_MASTER_AST_CF
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tristate "FSI master based on Aspeed ColdFire coprocessor"
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depends on GPIOLIB
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depends on GPIO_ASPEED
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---help---
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This option enables a FSI master using the AST2400 and AST2500 GPIO
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lines driven by the internal ColdFire coprocessor. This requires
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the corresponding machine specific ColdFire firmware to be available.
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config FSI_SCOM
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tristate "SCOM FSI client device driver"
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---help---
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@ -2,5 +2,6 @@
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obj-$(CONFIG_FSI) += fsi-core.o
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obj-$(CONFIG_FSI_MASTER_HUB) += fsi-master-hub.o
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obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o
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obj-$(CONFIG_FSI_MASTER_AST_CF) += fsi-master-ast-cf.o
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obj-$(CONFIG_FSI_SCOM) += fsi-scom.o
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obj-$(CONFIG_FSI_SBEFIFO) += fsi-sbefifo.o
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@ -0,0 +1,157 @@
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// SPDX-License-Identifier: GPL-2.0+
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#ifndef __CF_FSI_FW_H
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#define __CF_FSI_FW_H
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/*
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* uCode file layout
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*
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* 0000...03ff : m68k exception vectors
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* 0400...04ff : Header info & boot config block
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* 0500....... : Code & stack
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*/
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/*
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* Header info & boot config area
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*
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* The Header info is built into the ucode and provide version and
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* platform information.
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*
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* the Boot config needs to be adjusted by the ARM prior to starting
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* the ucode if the Command/Status area isn't at 0x320000 in CF space
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* (ie. beginning of SRAM).
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*/
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#define HDR_OFFSET 0x400
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/* Info: Signature & version */
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#define HDR_SYS_SIG 0x00 /* 2 bytes system signature */
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#define SYS_SIG_SHARED 0x5348
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#define SYS_SIG_SPLIT 0x5350
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#define HDR_FW_VERS 0x02 /* 2 bytes Major.Minor */
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#define HDR_API_VERS 0x04 /* 2 bytes Major.Minor */
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#define API_VERSION_MAJ 2 /* Current version */
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#define API_VERSION_MIN 1
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#define HDR_FW_OPTIONS 0x08 /* 4 bytes option flags */
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#define FW_OPTION_TRACE_EN 0x00000001 /* FW tracing enabled */
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#define FW_OPTION_CONT_CLOCK 0x00000002 /* Continuous clocking supported */
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#define HDR_FW_SIZE 0x10 /* 4 bytes size for combo image */
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/* Boot Config: Address of Command/Status area */
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#define HDR_CMD_STAT_AREA 0x80 /* 4 bytes CF address */
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#define HDR_FW_CONTROL 0x84 /* 4 bytes control flags */
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#define FW_CONTROL_CONT_CLOCK 0x00000002 /* Continuous clocking enabled */
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#define FW_CONTROL_DUMMY_RD 0x00000004 /* Extra dummy read (AST2400) */
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#define FW_CONTROL_USE_STOP 0x00000008 /* Use STOP instructions */
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#define HDR_CLOCK_GPIO_VADDR 0x90 /* 2 bytes offset from GPIO base */
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#define HDR_CLOCK_GPIO_DADDR 0x92 /* 2 bytes offset from GPIO base */
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#define HDR_DATA_GPIO_VADDR 0x94 /* 2 bytes offset from GPIO base */
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#define HDR_DATA_GPIO_DADDR 0x96 /* 2 bytes offset from GPIO base */
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#define HDR_TRANS_GPIO_VADDR 0x98 /* 2 bytes offset from GPIO base */
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#define HDR_TRANS_GPIO_DADDR 0x9a /* 2 bytes offset from GPIO base */
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#define HDR_CLOCK_GPIO_BIT 0x9c /* 1 byte bit number */
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#define HDR_DATA_GPIO_BIT 0x9d /* 1 byte bit number */
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#define HDR_TRANS_GPIO_BIT 0x9e /* 1 byte bit number */
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/*
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* Command/Status area layout: Main part
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*/
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/* Command/Status register:
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*
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* +---------------------------+
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* | STAT | RLEN | CLEN | CMD |
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* | 8 | 8 | 8 | 8 |
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* +---------------------------+
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* | | | |
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* status | | |
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* Response len | |
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* (in bits) | |
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* | |
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* Command len |
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* (in bits) |
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* |
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* Command code
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*
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* Due to the big endian layout, that means that a byte read will
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* return the status byte
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*/
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#define CMD_STAT_REG 0x00
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#define CMD_REG_CMD_MASK 0x000000ff
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#define CMD_REG_CMD_SHIFT 0
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#define CMD_NONE 0x00
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#define CMD_COMMAND 0x01
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#define CMD_BREAK 0x02
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#define CMD_IDLE_CLOCKS 0x03 /* clen = #clocks */
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#define CMD_INVALID 0xff
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#define CMD_REG_CLEN_MASK 0x0000ff00
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#define CMD_REG_CLEN_SHIFT 8
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#define CMD_REG_RLEN_MASK 0x00ff0000
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#define CMD_REG_RLEN_SHIFT 16
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#define CMD_REG_STAT_MASK 0xff000000
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#define CMD_REG_STAT_SHIFT 24
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#define STAT_WORKING 0x00
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#define STAT_COMPLETE 0x01
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#define STAT_ERR_INVAL_CMD 0x80
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#define STAT_ERR_INVAL_IRQ 0x81
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#define STAT_ERR_MTOE 0x82
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/* Response tag & CRC */
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#define STAT_RTAG 0x04
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/* Response CRC */
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#define STAT_RCRC 0x05
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/* Echo and Send delay */
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#define ECHO_DLY_REG 0x08
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#define SEND_DLY_REG 0x09
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/* Command data area
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*
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* Last byte of message must be left aligned
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*/
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#define CMD_DATA 0x10 /* 64 bit of data */
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/* Response data area, right aligned, unused top bits are 1 */
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#define RSP_DATA 0x20 /* 32 bit of data */
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/* Misc */
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#define INT_CNT 0x30 /* 32-bit interrupt count */
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#define BAD_INT_VEC 0x34 /* 32-bit bad interrupt vector # */
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#define CF_STARTED 0x38 /* byte, set to -1 when copro started */
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#define CLK_CNT 0x3c /* 32-bit, clock count (debug only) */
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/*
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* SRAM layout: GPIO arbitration part
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*/
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#define ARB_REG 0x40
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#define ARB_ARM_REQ 0x01
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#define ARB_ARM_ACK 0x02
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/* Misc2 */
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#define CF_RESET_D0 0x50
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#define CF_RESET_D1 0x54
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#define BAD_INT_S0 0x58
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#define BAD_INT_S1 0x5c
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#define STOP_CNT 0x60
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/* Internal */
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/*
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* SRAM layout: Trace buffer (debug builds only)
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*/
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#define TRACEBUF 0x100
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#define TR_CLKOBIT0 0xc0
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#define TR_CLKOBIT1 0xc1
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#define TR_CLKOSTART 0x82
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#define TR_OLEN 0x83 /* + len */
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#define TR_CLKZ 0x84 /* + count */
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#define TR_CLKWSTART 0x85
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#define TR_CLKTAG 0x86 /* + tag */
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#define TR_CLKDATA 0x87 /* + len */
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#define TR_CLKCRC 0x88 /* + raw crc */
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#define TR_CLKIBIT0 0x90
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#define TR_CLKIBIT1 0x91
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#define TR_END 0xff
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#endif /* __CF_FSI_FW_H */
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@ -80,6 +80,7 @@ struct fsi_slave {
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struct fsi_master *master;
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int id;
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int link;
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int chip_id;
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uint32_t size; /* size of slave address space */
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u8 t_send_delay;
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u8 t_echo_delay;
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@ -717,6 +718,17 @@ static ssize_t slave_send_echo_store(struct device *dev,
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static DEVICE_ATTR(send_echo_delays, 0600,
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slave_send_echo_show, slave_send_echo_store);
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static ssize_t chip_id_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct fsi_slave *slave = to_fsi_slave(dev);
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return sprintf(buf, "%d\n", slave->chip_id);
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}
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static DEVICE_ATTR_RO(chip_id);
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static int fsi_slave_init(struct fsi_master *master, int link, uint8_t id)
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{
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uint32_t chip_id;
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@ -780,6 +792,14 @@ static int fsi_slave_init(struct fsi_master *master, int link, uint8_t id)
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slave->t_send_delay = 16;
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slave->t_echo_delay = 16;
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/* Get chip ID if any */
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slave->chip_id = -1;
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if (slave->dev.of_node) {
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uint32_t prop;
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if (!of_property_read_u32(slave->dev.of_node, "chip-id", &prop))
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slave->chip_id = prop;
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}
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rc = fsi_slave_set_smode(slave);
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if (rc) {
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dev_warn(&master->dev,
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@ -814,6 +834,10 @@ static int fsi_slave_init(struct fsi_master *master, int link, uint8_t id)
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if (rc)
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dev_warn(&slave->dev, "failed to create delay attr: %d\n", rc);
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rc = device_create_file(&slave->dev, &dev_attr_chip_id);
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if (rc)
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dev_warn(&slave->dev, "failed to create chip id: %d\n", rc);
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rc = fsi_slave_scan(slave);
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if (rc)
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dev_dbg(&master->dev, "failed during slave scan with: %d\n",
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|
|
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File diff suppressed because it is too large
Load Diff
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@ -136,16 +136,14 @@ struct sbefifo_user {
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static DEFINE_IDA(sbefifo_ida);
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static DEFINE_MUTEX(sbefifo_ffdc_mutex);
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static void sbefifo_dump_ffdc(struct device *dev, const __be32 *ffdc,
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size_t ffdc_sz, bool internal)
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static void __sbefifo_dump_ffdc(struct device *dev, const __be32 *ffdc,
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size_t ffdc_sz, bool internal)
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{
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int pack = 0;
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#define FFDC_LSIZE 60
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static char ffdc_line[FFDC_LSIZE];
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char *p = ffdc_line;
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||||
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||||
mutex_lock(&sbefifo_ffdc_mutex);
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||||
while (ffdc_sz) {
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||||
u32 w0, w1, w2, i;
|
||||
if (ffdc_sz < 3) {
|
||||
|
|
@ -194,6 +192,13 @@ static void sbefifo_dump_ffdc(struct device *dev, const __be32 *ffdc,
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|||
}
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dev_warn(dev, "+-------------------------------------------+\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void sbefifo_dump_ffdc(struct device *dev, const __be32 *ffdc,
|
||||
size_t ffdc_sz, bool internal)
|
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{
|
||||
mutex_lock(&sbefifo_ffdc_mutex);
|
||||
__sbefifo_dump_ffdc(dev, ffdc, ffdc_sz, internal);
|
||||
mutex_unlock(&sbefifo_ffdc_mutex);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <asm/div64.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/gpio/aspeed.h>
|
||||
#include <linux/hashtable.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
|
|
@ -22,6 +23,15 @@
|
|||
#include <linux/spinlock.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
/*
|
||||
* These two headers aren't meant to be used by GPIO drivers. We need
|
||||
* them in order to access gpio_chip_hwgpio() which we need to implement
|
||||
* the aspeed specific API which allows the coprocessor to request
|
||||
* access to some GPIOs and to arbitrate between coprocessor and ARM.
|
||||
*/
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include "gpiolib.h"
|
||||
|
||||
struct aspeed_bank_props {
|
||||
unsigned int bank;
|
||||
u32 input;
|
||||
|
|
@ -56,83 +66,130 @@ struct aspeed_gpio {
|
|||
struct clk *clk;
|
||||
|
||||
u32 *dcache;
|
||||
u8 *cf_copro_bankmap;
|
||||
};
|
||||
|
||||
struct aspeed_gpio_bank {
|
||||
uint16_t val_regs;
|
||||
uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
|
||||
* +4: Rd/Wr: Direction (0=in, 1=out)
|
||||
*/
|
||||
uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */
|
||||
uint16_t irq_regs;
|
||||
uint16_t debounce_regs;
|
||||
uint16_t tolerance_regs;
|
||||
uint16_t cmdsrc_regs;
|
||||
const char names[4][3];
|
||||
};
|
||||
|
||||
/*
|
||||
* Note: The "value" register returns the input value sampled on the
|
||||
* line even when the GPIO is configured as an output. Since
|
||||
* that input goes through synchronizers, writing, then reading
|
||||
* back may not return the written value right away.
|
||||
*
|
||||
* The "rdata" register returns the content of the write latch
|
||||
* and thus can be used to read back what was last written
|
||||
* reliably.
|
||||
*/
|
||||
|
||||
static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
|
||||
|
||||
static const struct aspeed_gpio_copro_ops *copro_ops;
|
||||
static void *copro_data;
|
||||
|
||||
static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
|
||||
{
|
||||
.val_regs = 0x0000,
|
||||
.rdata_reg = 0x00c0,
|
||||
.irq_regs = 0x0008,
|
||||
.debounce_regs = 0x0040,
|
||||
.tolerance_regs = 0x001c,
|
||||
.cmdsrc_regs = 0x0060,
|
||||
.names = { "A", "B", "C", "D" },
|
||||
},
|
||||
{
|
||||
.val_regs = 0x0020,
|
||||
.rdata_reg = 0x00c4,
|
||||
.irq_regs = 0x0028,
|
||||
.debounce_regs = 0x0048,
|
||||
.tolerance_regs = 0x003c,
|
||||
.cmdsrc_regs = 0x0068,
|
||||
.names = { "E", "F", "G", "H" },
|
||||
},
|
||||
{
|
||||
.val_regs = 0x0070,
|
||||
.rdata_reg = 0x00c8,
|
||||
.irq_regs = 0x0098,
|
||||
.debounce_regs = 0x00b0,
|
||||
.tolerance_regs = 0x00ac,
|
||||
.cmdsrc_regs = 0x0090,
|
||||
.names = { "I", "J", "K", "L" },
|
||||
},
|
||||
{
|
||||
.val_regs = 0x0078,
|
||||
.rdata_reg = 0x00cc,
|
||||
.irq_regs = 0x00e8,
|
||||
.debounce_regs = 0x0100,
|
||||
.tolerance_regs = 0x00fc,
|
||||
.cmdsrc_regs = 0x00e0,
|
||||
.names = { "M", "N", "O", "P" },
|
||||
},
|
||||
{
|
||||
.val_regs = 0x0080,
|
||||
.rdata_reg = 0x00d0,
|
||||
.irq_regs = 0x0118,
|
||||
.debounce_regs = 0x0130,
|
||||
.tolerance_regs = 0x012c,
|
||||
.cmdsrc_regs = 0x0110,
|
||||
.names = { "Q", "R", "S", "T" },
|
||||
},
|
||||
{
|
||||
.val_regs = 0x0088,
|
||||
.rdata_reg = 0x00d4,
|
||||
.irq_regs = 0x0148,
|
||||
.debounce_regs = 0x0160,
|
||||
.tolerance_regs = 0x015c,
|
||||
.cmdsrc_regs = 0x0140,
|
||||
.names = { "U", "V", "W", "X" },
|
||||
},
|
||||
{
|
||||
.val_regs = 0x01E0,
|
||||
.rdata_reg = 0x00d8,
|
||||
.irq_regs = 0x0178,
|
||||
.debounce_regs = 0x0190,
|
||||
.tolerance_regs = 0x018c,
|
||||
.cmdsrc_regs = 0x0170,
|
||||
.names = { "Y", "Z", "AA", "AB" },
|
||||
},
|
||||
{
|
||||
.val_regs = 0x01e8,
|
||||
.rdata_reg = 0x00dc,
|
||||
.irq_regs = 0x01a8,
|
||||
.debounce_regs = 0x01c0,
|
||||
.tolerance_regs = 0x01bc,
|
||||
.cmdsrc_regs = 0x01a0,
|
||||
.names = { "AC", "", "", "" },
|
||||
},
|
||||
};
|
||||
|
||||
#define GPIO_BANK(x) ((x) >> 5)
|
||||
#define GPIO_OFFSET(x) ((x) & 0x1f)
|
||||
#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
|
||||
enum aspeed_gpio_reg {
|
||||
reg_val,
|
||||
reg_rdata,
|
||||
reg_dir,
|
||||
reg_irq_enable,
|
||||
reg_irq_type0,
|
||||
reg_irq_type1,
|
||||
reg_irq_type2,
|
||||
reg_irq_status,
|
||||
reg_debounce_sel1,
|
||||
reg_debounce_sel2,
|
||||
reg_tolerance,
|
||||
reg_cmdsrc0,
|
||||
reg_cmdsrc1,
|
||||
};
|
||||
|
||||
#define GPIO_DATA 0x00
|
||||
#define GPIO_DIR 0x04
|
||||
#define GPIO_VAL_VALUE 0x00
|
||||
#define GPIO_VAL_DIR 0x04
|
||||
|
||||
#define GPIO_IRQ_ENABLE 0x00
|
||||
#define GPIO_IRQ_TYPE0 0x04
|
||||
|
|
@ -143,6 +200,53 @@ static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
|
|||
#define GPIO_DEBOUNCE_SEL1 0x00
|
||||
#define GPIO_DEBOUNCE_SEL2 0x04
|
||||
|
||||
#define GPIO_CMDSRC_0 0x00
|
||||
#define GPIO_CMDSRC_1 0x04
|
||||
#define GPIO_CMDSRC_ARM 0
|
||||
#define GPIO_CMDSRC_LPC 1
|
||||
#define GPIO_CMDSRC_COLDFIRE 2
|
||||
#define GPIO_CMDSRC_RESERVED 3
|
||||
|
||||
/* This will be resolved at compile time */
|
||||
static inline void __iomem *bank_reg(struct aspeed_gpio *gpio,
|
||||
const struct aspeed_gpio_bank *bank,
|
||||
const enum aspeed_gpio_reg reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case reg_val:
|
||||
return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
|
||||
case reg_rdata:
|
||||
return gpio->base + bank->rdata_reg;
|
||||
case reg_dir:
|
||||
return gpio->base + bank->val_regs + GPIO_VAL_DIR;
|
||||
case reg_irq_enable:
|
||||
return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
|
||||
case reg_irq_type0:
|
||||
return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
|
||||
case reg_irq_type1:
|
||||
return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
|
||||
case reg_irq_type2:
|
||||
return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
|
||||
case reg_irq_status:
|
||||
return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
|
||||
case reg_debounce_sel1:
|
||||
return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
|
||||
case reg_debounce_sel2:
|
||||
return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
|
||||
case reg_tolerance:
|
||||
return gpio->base + bank->tolerance_regs;
|
||||
case reg_cmdsrc0:
|
||||
return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;
|
||||
case reg_cmdsrc1:
|
||||
return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;
|
||||
}
|
||||
BUG_ON(1);
|
||||
}
|
||||
|
||||
#define GPIO_BANK(x) ((x) >> 5)
|
||||
#define GPIO_OFFSET(x) ((x) & 0x1f)
|
||||
#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
|
||||
|
||||
#define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o))
|
||||
#define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1)
|
||||
#define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0)
|
||||
|
|
@ -201,18 +305,80 @@ static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
|
|||
return !props || (props->output & GPIO_BIT(offset));
|
||||
}
|
||||
|
||||
static void __iomem *bank_val_reg(struct aspeed_gpio *gpio,
|
||||
const struct aspeed_gpio_bank *bank,
|
||||
unsigned int reg)
|
||||
static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio,
|
||||
const struct aspeed_gpio_bank *bank,
|
||||
int bindex, int cmdsrc)
|
||||
{
|
||||
return gpio->base + bank->val_regs + reg;
|
||||
void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0);
|
||||
void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1);
|
||||
u32 bit, reg;
|
||||
|
||||
/*
|
||||
* Each register controls 4 banks, so take the bottom 2
|
||||
* bits of the bank index, and use them to select the
|
||||
* right control bit (0, 8, 16 or 24).
|
||||
*/
|
||||
bit = BIT((bindex & 3) << 3);
|
||||
|
||||
/* Source 1 first to avoid illegal 11 combination */
|
||||
reg = ioread32(c1);
|
||||
if (cmdsrc & 2)
|
||||
reg |= bit;
|
||||
else
|
||||
reg &= ~bit;
|
||||
iowrite32(reg, c1);
|
||||
|
||||
/* Then Source 0 */
|
||||
reg = ioread32(c0);
|
||||
if (cmdsrc & 1)
|
||||
reg |= bit;
|
||||
else
|
||||
reg &= ~bit;
|
||||
iowrite32(reg, c0);
|
||||
}
|
||||
|
||||
static void __iomem *bank_irq_reg(struct aspeed_gpio *gpio,
|
||||
const struct aspeed_gpio_bank *bank,
|
||||
unsigned int reg)
|
||||
static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio,
|
||||
unsigned int offset)
|
||||
{
|
||||
return gpio->base + bank->irq_regs + reg;
|
||||
const struct aspeed_gpio_bank *bank = to_bank(offset);
|
||||
|
||||
if (!copro_ops || !gpio->cf_copro_bankmap)
|
||||
return false;
|
||||
if (!gpio->cf_copro_bankmap[offset >> 3])
|
||||
return false;
|
||||
if (!copro_ops->request_access)
|
||||
return false;
|
||||
|
||||
/* Pause the coprocessor */
|
||||
copro_ops->request_access(copro_data);
|
||||
|
||||
/* Change command source back to ARM */
|
||||
aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM);
|
||||
|
||||
/* Update cache */
|
||||
gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata));
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio,
|
||||
unsigned int offset)
|
||||
{
|
||||
const struct aspeed_gpio_bank *bank = to_bank(offset);
|
||||
|
||||
if (!copro_ops || !gpio->cf_copro_bankmap)
|
||||
return;
|
||||
if (!gpio->cf_copro_bankmap[offset >> 3])
|
||||
return;
|
||||
if (!copro_ops->release_access)
|
||||
return;
|
||||
|
||||
/* Change command source back to ColdFire */
|
||||
aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3,
|
||||
GPIO_CMDSRC_COLDFIRE);
|
||||
|
||||
/* Restart the coprocessor */
|
||||
copro_ops->release_access(copro_data);
|
||||
}
|
||||
|
||||
static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset)
|
||||
|
|
@ -220,8 +386,7 @@ static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset)
|
|||
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
|
||||
const struct aspeed_gpio_bank *bank = to_bank(offset);
|
||||
|
||||
return !!(ioread32(bank_val_reg(gpio, bank, GPIO_DATA))
|
||||
& GPIO_BIT(offset));
|
||||
return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset));
|
||||
}
|
||||
|
||||
static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
|
||||
|
|
@ -232,7 +397,7 @@ static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
|
|||
void __iomem *addr;
|
||||
u32 reg;
|
||||
|
||||
addr = bank_val_reg(gpio, bank, GPIO_DATA);
|
||||
addr = bank_reg(gpio, bank, reg_val);
|
||||
reg = gpio->dcache[GPIO_BANK(offset)];
|
||||
|
||||
if (val)
|
||||
|
|
@ -249,11 +414,15 @@ static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
|
|||
{
|
||||
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
|
||||
unsigned long flags;
|
||||
bool copro;
|
||||
|
||||
spin_lock_irqsave(&gpio->lock, flags);
|
||||
copro = aspeed_gpio_copro_request(gpio, offset);
|
||||
|
||||
__aspeed_gpio_set(gc, offset, val);
|
||||
|
||||
if (copro)
|
||||
aspeed_gpio_copro_release(gpio, offset);
|
||||
spin_unlock_irqrestore(&gpio->lock, flags);
|
||||
}
|
||||
|
||||
|
|
@ -261,7 +430,9 @@ static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
|
|||
{
|
||||
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
|
||||
const struct aspeed_gpio_bank *bank = to_bank(offset);
|
||||
void __iomem *addr = bank_reg(gpio, bank, reg_dir);
|
||||
unsigned long flags;
|
||||
bool copro;
|
||||
u32 reg;
|
||||
|
||||
if (!have_input(gpio, offset))
|
||||
|
|
@ -269,8 +440,13 @@ static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
|
|||
|
||||
spin_lock_irqsave(&gpio->lock, flags);
|
||||
|
||||
reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR));
|
||||
iowrite32(reg & ~GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR));
|
||||
reg = ioread32(addr);
|
||||
reg &= ~GPIO_BIT(offset);
|
||||
|
||||
copro = aspeed_gpio_copro_request(gpio, offset);
|
||||
iowrite32(reg, addr);
|
||||
if (copro)
|
||||
aspeed_gpio_copro_release(gpio, offset);
|
||||
|
||||
spin_unlock_irqrestore(&gpio->lock, flags);
|
||||
|
||||
|
|
@ -282,7 +458,9 @@ static int aspeed_gpio_dir_out(struct gpio_chip *gc,
|
|||
{
|
||||
struct aspeed_gpio *gpio = gpiochip_get_data(gc);
|
||||
const struct aspeed_gpio_bank *bank = to_bank(offset);
|
||||
void __iomem *addr = bank_reg(gpio, bank, reg_dir);
|
||||
unsigned long flags;
|
||||
bool copro;
|
||||
u32 reg;
|
||||
|
||||
if (!have_output(gpio, offset))
|
||||
|
|
@ -290,10 +468,15 @@ static int aspeed_gpio_dir_out(struct gpio_chip *gc,
|
|||
|
||||
spin_lock_irqsave(&gpio->lock, flags);
|
||||
|
||||
__aspeed_gpio_set(gc, offset, val);
|
||||
reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR));
|
||||
iowrite32(reg | GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR));
|
||||
reg = ioread32(addr);
|
||||
reg |= GPIO_BIT(offset);
|
||||
|
||||
copro = aspeed_gpio_copro_request(gpio, offset);
|
||||
__aspeed_gpio_set(gc, offset, val);
|
||||
iowrite32(reg, addr);
|
||||
|
||||
if (copro)
|
||||
aspeed_gpio_copro_release(gpio, offset);
|
||||
spin_unlock_irqrestore(&gpio->lock, flags);
|
||||
|
||||
return 0;
|
||||
|
|
@ -314,7 +497,7 @@ static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
|
|||
|
||||
spin_lock_irqsave(&gpio->lock, flags);
|
||||
|
||||
val = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)) & GPIO_BIT(offset);
|
||||
val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);
|
||||
|
||||
spin_unlock_irqrestore(&gpio->lock, flags);
|
||||
|
||||
|
|
@ -323,24 +506,23 @@ static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
|
|||
}
|
||||
|
||||
static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
|
||||
struct aspeed_gpio **gpio,
|
||||
const struct aspeed_gpio_bank **bank,
|
||||
u32 *bit)
|
||||
struct aspeed_gpio **gpio,
|
||||
const struct aspeed_gpio_bank **bank,
|
||||
u32 *bit, int *offset)
|
||||
{
|
||||
int offset;
|
||||
struct aspeed_gpio *internal;
|
||||
|
||||
offset = irqd_to_hwirq(d);
|
||||
*offset = irqd_to_hwirq(d);
|
||||
|
||||
internal = irq_data_get_irq_chip_data(d);
|
||||
|
||||
/* This might be a bit of a questionable place to check */
|
||||
if (!have_irq(internal, offset))
|
||||
if (!have_irq(internal, *offset))
|
||||
return -ENOTSUPP;
|
||||
|
||||
*gpio = internal;
|
||||
*bank = to_bank(offset);
|
||||
*bit = GPIO_BIT(offset);
|
||||
*bank = to_bank(*offset);
|
||||
*bit = GPIO_BIT(*offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -351,17 +533,23 @@ static void aspeed_gpio_irq_ack(struct irq_data *d)
|
|||
struct aspeed_gpio *gpio;
|
||||
unsigned long flags;
|
||||
void __iomem *status_addr;
|
||||
int rc, offset;
|
||||
bool copro;
|
||||
u32 bit;
|
||||
int rc;
|
||||
|
||||
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
|
||||
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
status_addr = bank_irq_reg(gpio, bank, GPIO_IRQ_STATUS);
|
||||
status_addr = bank_reg(gpio, bank, reg_irq_status);
|
||||
|
||||
spin_lock_irqsave(&gpio->lock, flags);
|
||||
copro = aspeed_gpio_copro_request(gpio, offset);
|
||||
|
||||
iowrite32(bit, status_addr);
|
||||
|
||||
if (copro)
|
||||
aspeed_gpio_copro_release(gpio, offset);
|
||||
spin_unlock_irqrestore(&gpio->lock, flags);
|
||||
}
|
||||
|
||||
|
|
@ -372,15 +560,17 @@ static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
|
|||
unsigned long flags;
|
||||
u32 reg, bit;
|
||||
void __iomem *addr;
|
||||
int rc;
|
||||
int rc, offset;
|
||||
bool copro;
|
||||
|
||||
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
|
||||
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
addr = bank_irq_reg(gpio, bank, GPIO_IRQ_ENABLE);
|
||||
addr = bank_reg(gpio, bank, reg_irq_enable);
|
||||
|
||||
spin_lock_irqsave(&gpio->lock, flags);
|
||||
copro = aspeed_gpio_copro_request(gpio, offset);
|
||||
|
||||
reg = ioread32(addr);
|
||||
if (set)
|
||||
|
|
@ -389,6 +579,8 @@ static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
|
|||
reg &= ~bit;
|
||||
iowrite32(reg, addr);
|
||||
|
||||
if (copro)
|
||||
aspeed_gpio_copro_release(gpio, offset);
|
||||
spin_unlock_irqrestore(&gpio->lock, flags);
|
||||
}
|
||||
|
||||
|
|
@ -413,9 +605,10 @@ static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
|
|||
struct aspeed_gpio *gpio;
|
||||
unsigned long flags;
|
||||
void __iomem *addr;
|
||||
int rc;
|
||||
int rc, offset;
|
||||
bool copro;
|
||||
|
||||
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit);
|
||||
rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
|
||||
if (rc)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
@ -441,22 +634,25 @@ static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
|
|||
}
|
||||
|
||||
spin_lock_irqsave(&gpio->lock, flags);
|
||||
copro = aspeed_gpio_copro_request(gpio, offset);
|
||||
|
||||
addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE0);
|
||||
addr = bank_reg(gpio, bank, reg_irq_type0);
|
||||
reg = ioread32(addr);
|
||||
reg = (reg & ~bit) | type0;
|
||||
iowrite32(reg, addr);
|
||||
|
||||
addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE1);
|
||||
addr = bank_reg(gpio, bank, reg_irq_type1);
|
||||
reg = ioread32(addr);
|
||||
reg = (reg & ~bit) | type1;
|
||||
iowrite32(reg, addr);
|
||||
|
||||
addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE2);
|
||||
addr = bank_reg(gpio, bank, reg_irq_type2);
|
||||
reg = ioread32(addr);
|
||||
reg = (reg & ~bit) | type2;
|
||||
iowrite32(reg, addr);
|
||||
|
||||
if (copro)
|
||||
aspeed_gpio_copro_release(gpio, offset);
|
||||
spin_unlock_irqrestore(&gpio->lock, flags);
|
||||
|
||||
irq_set_handler_locked(d, handler);
|
||||
|
|
@ -477,7 +673,7 @@ static void aspeed_gpio_irq_handler(struct irq_desc *desc)
|
|||
for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) {
|
||||
const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
|
||||
|
||||
reg = ioread32(bank_irq_reg(data, bank, GPIO_IRQ_STATUS));
|
||||
reg = ioread32(bank_reg(data, bank, reg_irq_status));
|
||||
|
||||
for_each_set_bit(p, ®, 32) {
|
||||
girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
|
||||
|
|
@ -549,21 +745,27 @@ static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip,
|
|||
unsigned int offset, bool enable)
|
||||
{
|
||||
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
|
||||
const struct aspeed_gpio_bank *bank;
|
||||
unsigned long flags;
|
||||
void __iomem *treg;
|
||||
bool copro;
|
||||
u32 val;
|
||||
|
||||
bank = to_bank(offset);
|
||||
treg = bank_reg(gpio, to_bank(offset), reg_tolerance);
|
||||
|
||||
spin_lock_irqsave(&gpio->lock, flags);
|
||||
val = readl(gpio->base + bank->tolerance_regs);
|
||||
copro = aspeed_gpio_copro_request(gpio, offset);
|
||||
|
||||
val = readl(treg);
|
||||
|
||||
if (enable)
|
||||
val |= GPIO_BIT(offset);
|
||||
else
|
||||
val &= ~GPIO_BIT(offset);
|
||||
|
||||
writel(val, gpio->base + bank->tolerance_regs);
|
||||
writel(val, treg);
|
||||
|
||||
if (copro)
|
||||
aspeed_gpio_copro_release(gpio, offset);
|
||||
spin_unlock_irqrestore(&gpio->lock, flags);
|
||||
|
||||
return 0;
|
||||
|
|
@ -582,13 +784,6 @@ static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
|
|||
pinctrl_gpio_free(chip->base + offset);
|
||||
}
|
||||
|
||||
static inline void __iomem *bank_debounce_reg(struct aspeed_gpio *gpio,
|
||||
const struct aspeed_gpio_bank *bank,
|
||||
unsigned int reg)
|
||||
{
|
||||
return gpio->base + bank->debounce_regs + reg;
|
||||
}
|
||||
|
||||
static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
|
||||
u32 *cycles)
|
||||
{
|
||||
|
|
@ -666,11 +861,14 @@ static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
|
|||
void __iomem *addr;
|
||||
u32 val;
|
||||
|
||||
addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL1);
|
||||
/* Note: Debounce timer isn't under control of the command
|
||||
* source registers, so no need to sync with the coprocessor
|
||||
*/
|
||||
addr = bank_reg(gpio, bank, reg_debounce_sel1);
|
||||
val = ioread32(addr);
|
||||
iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr);
|
||||
|
||||
addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL2);
|
||||
addr = bank_reg(gpio, bank, reg_debounce_sel2);
|
||||
val = ioread32(addr);
|
||||
iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr);
|
||||
}
|
||||
|
|
@ -812,6 +1010,111 @@ static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
|
|||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
/**
|
||||
* aspeed_gpio_copro_set_ops - Sets the callbacks used for handhsaking with
|
||||
* the coprocessor for shared GPIO banks
|
||||
* @ops: The callbacks
|
||||
* @data: Pointer passed back to the callbacks
|
||||
*/
|
||||
int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data)
|
||||
{
|
||||
copro_data = data;
|
||||
copro_ops = ops;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops);
|
||||
|
||||
/**
|
||||
* aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
|
||||
* bank gets marked and any access from the ARM will
|
||||
* result in handshaking via callbacks.
|
||||
* @desc: The GPIO to be marked
|
||||
* @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
|
||||
* @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
|
||||
* @bit: If non-NULL, returns the bit number of the GPIO in the registers
|
||||
*/
|
||||
int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc,
|
||||
u16 *vreg_offset, u16 *dreg_offset, u8 *bit)
|
||||
{
|
||||
struct gpio_chip *chip = gpiod_to_chip(desc);
|
||||
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
|
||||
int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
|
||||
const struct aspeed_gpio_bank *bank = to_bank(offset);
|
||||
unsigned long flags;
|
||||
|
||||
if (!gpio->cf_copro_bankmap)
|
||||
gpio->cf_copro_bankmap = kzalloc(gpio->config->nr_gpios >> 3, GFP_KERNEL);
|
||||
if (!gpio->cf_copro_bankmap)
|
||||
return -ENOMEM;
|
||||
if (offset < 0 || offset > gpio->config->nr_gpios)
|
||||
return -EINVAL;
|
||||
bindex = offset >> 3;
|
||||
|
||||
spin_lock_irqsave(&gpio->lock, flags);
|
||||
|
||||
/* Sanity check, this shouldn't happen */
|
||||
if (gpio->cf_copro_bankmap[bindex] == 0xff) {
|
||||
rc = -EIO;
|
||||
goto bail;
|
||||
}
|
||||
gpio->cf_copro_bankmap[bindex]++;
|
||||
|
||||
/* Switch command source */
|
||||
if (gpio->cf_copro_bankmap[bindex] == 1)
|
||||
aspeed_gpio_change_cmd_source(gpio, bank, bindex,
|
||||
GPIO_CMDSRC_COLDFIRE);
|
||||
|
||||
if (vreg_offset)
|
||||
*vreg_offset = bank->val_regs;
|
||||
if (dreg_offset)
|
||||
*dreg_offset = bank->rdata_reg;
|
||||
if (bit)
|
||||
*bit = GPIO_OFFSET(offset);
|
||||
bail:
|
||||
spin_unlock_irqrestore(&gpio->lock, flags);
|
||||
return rc;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio);
|
||||
|
||||
/**
|
||||
* aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
|
||||
* @desc: The GPIO to be marked
|
||||
*/
|
||||
int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc)
|
||||
{
|
||||
struct gpio_chip *chip = gpiod_to_chip(desc);
|
||||
struct aspeed_gpio *gpio = gpiochip_get_data(chip);
|
||||
int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
|
||||
const struct aspeed_gpio_bank *bank = to_bank(offset);
|
||||
unsigned long flags;
|
||||
|
||||
if (!gpio->cf_copro_bankmap)
|
||||
return -ENXIO;
|
||||
|
||||
if (offset < 0 || offset > gpio->config->nr_gpios)
|
||||
return -EINVAL;
|
||||
bindex = offset >> 3;
|
||||
|
||||
spin_lock_irqsave(&gpio->lock, flags);
|
||||
|
||||
/* Sanity check, this shouldn't happen */
|
||||
if (gpio->cf_copro_bankmap[bindex] == 0) {
|
||||
rc = -EIO;
|
||||
goto bail;
|
||||
}
|
||||
gpio->cf_copro_bankmap[bindex]--;
|
||||
|
||||
/* Switch command source */
|
||||
if (gpio->cf_copro_bankmap[bindex] == 0)
|
||||
aspeed_gpio_change_cmd_source(gpio, bank, bindex,
|
||||
GPIO_CMDSRC_ARM);
|
||||
bail:
|
||||
spin_unlock_irqrestore(&gpio->lock, flags);
|
||||
return rc;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio);
|
||||
|
||||
/*
|
||||
* Any banks not specified in a struct aspeed_bank_props array are assumed to
|
||||
* have the properties:
|
||||
|
|
@ -902,11 +1205,18 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
|
|||
if (!gpio->dcache)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Populate it with initial values read from the HW */
|
||||
/*
|
||||
* Populate it with initial values read from the HW and switch
|
||||
* all command sources to the ARM by default
|
||||
*/
|
||||
for (i = 0; i < banks; i++) {
|
||||
const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
|
||||
gpio->dcache[i] = ioread32(gpio->base + bank->val_regs +
|
||||
GPIO_DATA);
|
||||
void __iomem *addr = bank_reg(gpio, bank, reg_rdata);
|
||||
gpio->dcache[i] = ioread32(addr);
|
||||
aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM);
|
||||
aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM);
|
||||
aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM);
|
||||
aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM);
|
||||
}
|
||||
|
||||
rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
|
||||
|
|
|
|||
|
|
@ -696,6 +696,10 @@ extern void devm_free_pages(struct device *dev, unsigned long addr);
|
|||
|
||||
void __iomem *devm_ioremap_resource(struct device *dev, struct resource *res);
|
||||
|
||||
void __iomem *devm_of_iomap(struct device *dev,
|
||||
struct device_node *node, int index,
|
||||
resource_size_t *size);
|
||||
|
||||
/* allows to add/remove a custom action to devres stack */
|
||||
int devm_add_action(struct device *dev, void (*action)(void *), void *data);
|
||||
void devm_remove_action(struct device *dev, void (*action)(void *), void *data);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,15 @@
|
|||
#ifndef __GPIO_ASPEED_H
|
||||
#define __GPIO_ASPEED_H
|
||||
|
||||
struct aspeed_gpio_copro_ops {
|
||||
int (*request_access)(void *data);
|
||||
int (*release_access)(void *data);
|
||||
};
|
||||
|
||||
int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc,
|
||||
u16 *vreg_offset, u16 *dreg_offset, u8 *bit);
|
||||
int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc);
|
||||
int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data);
|
||||
|
||||
|
||||
#endif /* __GPIO_ASPEED_H */
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
|
||||
#undef TRACE_SYSTEM
|
||||
#define TRACE_SYSTEM fsi_master_ast_cf
|
||||
|
||||
#if !defined(_TRACE_FSI_MASTER_ACF_H) || defined(TRACE_HEADER_MULTI_READ)
|
||||
#define _TRACE_FSI_MASTER_ACF_H
|
||||
|
||||
#include <linux/tracepoint.h>
|
||||
|
||||
TRACE_EVENT(fsi_master_acf_copro_command,
|
||||
TP_PROTO(const struct fsi_master_acf *master, uint32_t op),
|
||||
TP_ARGS(master, op),
|
||||
TP_STRUCT__entry(
|
||||
__field(int, master_idx)
|
||||
__field(uint32_t, op)
|
||||
),
|
||||
TP_fast_assign(
|
||||
__entry->master_idx = master->master.idx;
|
||||
__entry->op = op;
|
||||
),
|
||||
TP_printk("fsi-acf%d command %08x",
|
||||
__entry->master_idx, __entry->op
|
||||
)
|
||||
);
|
||||
|
||||
TRACE_EVENT(fsi_master_acf_send_request,
|
||||
TP_PROTO(const struct fsi_master_acf *master, const struct fsi_msg *cmd, u8 rbits),
|
||||
TP_ARGS(master, cmd, rbits),
|
||||
TP_STRUCT__entry(
|
||||
__field(int, master_idx)
|
||||
__field(uint64_t, msg)
|
||||
__field(u8, bits)
|
||||
__field(u8, rbits)
|
||||
),
|
||||
TP_fast_assign(
|
||||
__entry->master_idx = master->master.idx;
|
||||
__entry->msg = cmd->msg;
|
||||
__entry->bits = cmd->bits;
|
||||
__entry->rbits = rbits;
|
||||
),
|
||||
TP_printk("fsi-acf%d cmd: %016llx/%d/%d",
|
||||
__entry->master_idx, (unsigned long long)__entry->msg,
|
||||
__entry->bits, __entry->rbits
|
||||
)
|
||||
);
|
||||
|
||||
TRACE_EVENT(fsi_master_acf_copro_response,
|
||||
TP_PROTO(const struct fsi_master_acf *master, u8 rtag, u8 rcrc, __be32 rdata, bool crc_ok),
|
||||
TP_ARGS(master, rtag, rcrc, rdata, crc_ok),
|
||||
TP_STRUCT__entry(
|
||||
__field(int, master_idx)
|
||||
__field(u8, rtag)
|
||||
__field(u8, rcrc)
|
||||
__field(u32, rdata)
|
||||
__field(bool, crc_ok)
|
||||
),
|
||||
TP_fast_assign(
|
||||
__entry->master_idx = master->master.idx;
|
||||
__entry->rtag = rtag;
|
||||
__entry->rcrc = rcrc;
|
||||
__entry->rdata = be32_to_cpu(rdata);
|
||||
__entry->crc_ok = crc_ok;
|
||||
),
|
||||
TP_printk("fsi-acf%d rsp: tag=%04x crc=%04x data=%08x %c\n",
|
||||
__entry->master_idx, __entry->rtag, __entry->rcrc,
|
||||
__entry->rdata, __entry->crc_ok ? ' ' : '!'
|
||||
)
|
||||
);
|
||||
|
||||
TRACE_EVENT(fsi_master_acf_crc_rsp_error,
|
||||
TP_PROTO(const struct fsi_master_acf *master, int retries),
|
||||
TP_ARGS(master, retries),
|
||||
TP_STRUCT__entry(
|
||||
__field(int, master_idx)
|
||||
__field(int, retries)
|
||||
),
|
||||
TP_fast_assign(
|
||||
__entry->master_idx = master->master.idx;
|
||||
__entry->retries = retries;
|
||||
),
|
||||
TP_printk("fsi-acf%d CRC error in response retry %d",
|
||||
__entry->master_idx, __entry->retries
|
||||
)
|
||||
);
|
||||
|
||||
TRACE_EVENT(fsi_master_acf_poll_response_busy,
|
||||
TP_PROTO(const struct fsi_master_acf *master, int busy_count),
|
||||
TP_ARGS(master, busy_count),
|
||||
TP_STRUCT__entry(
|
||||
__field(int, master_idx)
|
||||
__field(int, busy_count)
|
||||
),
|
||||
TP_fast_assign(
|
||||
__entry->master_idx = master->master.idx;
|
||||
__entry->busy_count = busy_count;
|
||||
),
|
||||
TP_printk("fsi-acf%d: device reported busy %d times",
|
||||
__entry->master_idx, __entry->busy_count
|
||||
)
|
||||
);
|
||||
|
||||
TRACE_EVENT(fsi_master_acf_cmd_abs_addr,
|
||||
TP_PROTO(const struct fsi_master_acf *master, u32 addr),
|
||||
TP_ARGS(master, addr),
|
||||
TP_STRUCT__entry(
|
||||
__field(int, master_idx)
|
||||
__field(u32, addr)
|
||||
),
|
||||
TP_fast_assign(
|
||||
__entry->master_idx = master->master.idx;
|
||||
__entry->addr = addr;
|
||||
),
|
||||
TP_printk("fsi-acf%d: Sending ABS_ADR %06x",
|
||||
__entry->master_idx, __entry->addr
|
||||
)
|
||||
);
|
||||
|
||||
TRACE_EVENT(fsi_master_acf_cmd_rel_addr,
|
||||
TP_PROTO(const struct fsi_master_acf *master, u32 rel_addr),
|
||||
TP_ARGS(master, rel_addr),
|
||||
TP_STRUCT__entry(
|
||||
__field(int, master_idx)
|
||||
__field(u32, rel_addr)
|
||||
),
|
||||
TP_fast_assign(
|
||||
__entry->master_idx = master->master.idx;
|
||||
__entry->rel_addr = rel_addr;
|
||||
),
|
||||
TP_printk("fsi-acf%d: Sending REL_ADR %03x",
|
||||
__entry->master_idx, __entry->rel_addr
|
||||
)
|
||||
);
|
||||
|
||||
TRACE_EVENT(fsi_master_acf_cmd_same_addr,
|
||||
TP_PROTO(const struct fsi_master_acf *master),
|
||||
TP_ARGS(master),
|
||||
TP_STRUCT__entry(
|
||||
__field(int, master_idx)
|
||||
),
|
||||
TP_fast_assign(
|
||||
__entry->master_idx = master->master.idx;
|
||||
),
|
||||
TP_printk("fsi-acf%d: Sending SAME_ADR",
|
||||
__entry->master_idx
|
||||
)
|
||||
);
|
||||
|
||||
#endif /* _TRACE_FSI_MASTER_ACF_H */
|
||||
|
||||
#include <trace/define_trace.h>
|
||||
36
lib/devres.c
36
lib/devres.c
|
|
@ -4,6 +4,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/gfp.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
enum devm_ioremap_type {
|
||||
DEVM_IOREMAP = 0,
|
||||
|
|
@ -162,6 +163,41 @@ void __iomem *devm_ioremap_resource(struct device *dev, struct resource *res)
|
|||
}
|
||||
EXPORT_SYMBOL(devm_ioremap_resource);
|
||||
|
||||
/*
|
||||
* devm_of_iomap - Requests a resource and maps the memory mapped IO
|
||||
* for a given device_node managed by a given device
|
||||
*
|
||||
* Checks that a resource is a valid memory region, requests the memory
|
||||
* region and ioremaps it. All operations are managed and will be undone
|
||||
* on driver detach of the device.
|
||||
*
|
||||
* This is to be used when a device requests/maps resources described
|
||||
* by other device tree nodes (children or otherwise).
|
||||
*
|
||||
* @dev: The device "managing" the resource
|
||||
* @node: The device-tree node where the resource resides
|
||||
* @index: index of the MMIO range in the "reg" property
|
||||
* @size: Returns the size of the resource (pass NULL if not needed)
|
||||
* Returns a pointer to the requested and mapped memory or an ERR_PTR() encoded
|
||||
* error code on failure. Usage example:
|
||||
*
|
||||
* base = devm_of_iomap(&pdev->dev, node, 0, NULL);
|
||||
* if (IS_ERR(base))
|
||||
* return PTR_ERR(base);
|
||||
*/
|
||||
void __iomem *devm_of_iomap(struct device *dev, struct device_node *node, int index,
|
||||
resource_size_t *size)
|
||||
{
|
||||
struct resource res;
|
||||
|
||||
if (of_address_to_resource(node, index, &res))
|
||||
return IOMEM_ERR_PTR(-EINVAL);
|
||||
if (size)
|
||||
*size = resource_size(&res);
|
||||
return devm_ioremap_resource(dev, &res);
|
||||
}
|
||||
EXPORT_SYMBOL(devm_of_iomap);
|
||||
|
||||
#ifdef CONFIG_HAS_IOPORT_MAP
|
||||
/*
|
||||
* Generic iomap devres
|
||||
|
|
|
|||
Loading…
Reference in New Issue