Merge branch 'drm-fixes-4.9' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
A few more fixes for 4.9. * 'drm-fixes-4.9' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: add some error handling to amdgpu_init v2 drm/amd: fix scheduler fence teardown order v2 drm/amd/powerplay: don't succeed in getters if fan is missing drm/amdgpu: make sure ddc_bus is valid in connector unregister drm/radeon: Fix kernel panic on shutdown drm/amdgpu: disable runtime pm in certain cases drm/radeon: disable runtime pm in certain cases drm/amdgpu: add support for new smc firmware on iceland drm/amdgpu: add support for new smc firmware on tonga
This commit is contained in:
commit
672c989158
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@ -795,10 +795,19 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
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if (!adev->pm.fw) {
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switch (adev->asic_type) {
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case CHIP_TOPAZ:
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strcpy(fw_name, "amdgpu/topaz_smc.bin");
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if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
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((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
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((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87)))
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strcpy(fw_name, "amdgpu/topaz_k_smc.bin");
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else
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strcpy(fw_name, "amdgpu/topaz_smc.bin");
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break;
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case CHIP_TONGA:
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strcpy(fw_name, "amdgpu/tonga_smc.bin");
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if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) ||
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((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1)))
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strcpy(fw_name, "amdgpu/tonga_k_smc.bin");
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else
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strcpy(fw_name, "amdgpu/tonga_smc.bin");
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break;
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case CHIP_FIJI:
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strcpy(fw_name, "amdgpu/fiji_smc.bin");
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@ -769,7 +769,7 @@ static void amdgpu_connector_unregister(struct drm_connector *connector)
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{
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struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
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if (amdgpu_connector->ddc_bus->has_aux) {
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if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
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drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
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amdgpu_connector->ddc_bus->has_aux = false;
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}
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@ -735,8 +735,20 @@ static struct pci_driver amdgpu_kms_pci_driver = {
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static int __init amdgpu_init(void)
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{
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amdgpu_sync_init();
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amdgpu_fence_slab_init();
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int r;
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r = amdgpu_sync_init();
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if (r)
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goto error_sync;
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r = amdgpu_fence_slab_init();
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if (r)
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goto error_fence;
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r = amd_sched_fence_slab_init();
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if (r)
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goto error_sched;
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if (vgacon_text_force()) {
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DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
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return -EINVAL;
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@ -748,6 +760,15 @@ static int __init amdgpu_init(void)
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amdgpu_register_atpx_handler();
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/* let modprobe override vga console setting */
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return drm_pci_init(driver, pdriver);
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error_sched:
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amdgpu_fence_slab_fini();
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error_fence:
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amdgpu_sync_fini();
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error_sync:
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return r;
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}
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static void __exit amdgpu_exit(void)
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@ -756,6 +777,7 @@ static void __exit amdgpu_exit(void)
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drm_pci_exit(driver, pdriver);
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amdgpu_unregister_atpx_handler();
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amdgpu_sync_fini();
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amd_sched_fence_slab_fini();
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amdgpu_fence_slab_fini();
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}
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@ -99,6 +99,8 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
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if ((amdgpu_runtime_pm != 0) &&
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amdgpu_has_atpx() &&
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(amdgpu_is_atpx_hybrid() ||
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amdgpu_has_atpx_dgpu_power_cntl()) &&
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((flags & AMD_IS_APU) == 0))
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flags |= AMD_IS_PX;
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@ -80,7 +80,9 @@
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#include "dce_virtual.h"
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MODULE_FIRMWARE("amdgpu/topaz_smc.bin");
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MODULE_FIRMWARE("amdgpu/topaz_k_smc.bin");
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MODULE_FIRMWARE("amdgpu/tonga_smc.bin");
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MODULE_FIRMWARE("amdgpu/tonga_k_smc.bin");
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MODULE_FIRMWARE("amdgpu/fiji_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
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@ -30,7 +30,7 @@ int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
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struct phm_fan_speed_info *fan_speed_info)
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{
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if (hwmgr->thermal_controller.fanInfo.bNoFan)
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return 0;
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return -ENODEV;
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fan_speed_info->supports_percent_read = true;
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fan_speed_info->supports_percent_write = true;
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@ -60,7 +60,7 @@ int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
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uint64_t tmp64;
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if (hwmgr->thermal_controller.fanInfo.bNoFan)
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return 0;
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return -ENODEV;
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duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
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CG_FDO_CTRL1, FMAX_DUTY100);
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@ -89,7 +89,7 @@ int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
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if (hwmgr->thermal_controller.fanInfo.bNoFan ||
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(hwmgr->thermal_controller.fanInfo.
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ucTachometerPulsesPerRevolution == 0))
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return 0;
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return -ENODEV;
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tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
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CG_TACH_STATUS, TACH_PERIOD);
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@ -34,9 +34,6 @@ static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity);
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static void amd_sched_wakeup(struct amd_gpu_scheduler *sched);
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static void amd_sched_process_job(struct fence *f, struct fence_cb *cb);
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struct kmem_cache *sched_fence_slab;
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atomic_t sched_fence_slab_ref = ATOMIC_INIT(0);
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/* Initialize a given run queue struct */
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static void amd_sched_rq_init(struct amd_sched_rq *rq)
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{
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@ -618,13 +615,6 @@ int amd_sched_init(struct amd_gpu_scheduler *sched,
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INIT_LIST_HEAD(&sched->ring_mirror_list);
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spin_lock_init(&sched->job_list_lock);
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atomic_set(&sched->hw_rq_count, 0);
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if (atomic_inc_return(&sched_fence_slab_ref) == 1) {
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sched_fence_slab = kmem_cache_create(
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"amd_sched_fence", sizeof(struct amd_sched_fence), 0,
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SLAB_HWCACHE_ALIGN, NULL);
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if (!sched_fence_slab)
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return -ENOMEM;
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}
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/* Each scheduler will run on a seperate kernel thread */
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sched->thread = kthread_run(amd_sched_main, sched, sched->name);
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@ -645,7 +635,4 @@ void amd_sched_fini(struct amd_gpu_scheduler *sched)
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{
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if (sched->thread)
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kthread_stop(sched->thread);
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rcu_barrier();
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if (atomic_dec_and_test(&sched_fence_slab_ref))
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kmem_cache_destroy(sched_fence_slab);
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}
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@ -30,9 +30,6 @@
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struct amd_gpu_scheduler;
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struct amd_sched_rq;
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extern struct kmem_cache *sched_fence_slab;
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extern atomic_t sched_fence_slab_ref;
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/**
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* A scheduler entity is a wrapper around a job queue or a group
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* of other entities. Entities take turns emitting jobs from their
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struct amd_sched_entity *entity);
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void amd_sched_entity_push_job(struct amd_sched_job *sched_job);
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int amd_sched_fence_slab_init(void);
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void amd_sched_fence_slab_fini(void);
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struct amd_sched_fence *amd_sched_fence_create(
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struct amd_sched_entity *s_entity, void *owner);
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void amd_sched_fence_scheduled(struct amd_sched_fence *fence);
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@ -27,6 +27,25 @@
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#include <drm/drmP.h>
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#include "gpu_scheduler.h"
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static struct kmem_cache *sched_fence_slab;
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int amd_sched_fence_slab_init(void)
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{
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sched_fence_slab = kmem_cache_create(
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"amd_sched_fence", sizeof(struct amd_sched_fence), 0,
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SLAB_HWCACHE_ALIGN, NULL);
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if (!sched_fence_slab)
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return -ENOMEM;
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return 0;
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}
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void amd_sched_fence_slab_fini(void)
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{
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rcu_barrier();
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kmem_cache_destroy(sched_fence_slab);
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}
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struct amd_sched_fence *amd_sched_fence_create(struct amd_sched_entity *entity,
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void *owner)
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{
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@ -931,7 +931,7 @@ static void radeon_connector_unregister(struct drm_connector *connector)
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{
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struct radeon_connector *radeon_connector = to_radeon_connector(connector);
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if (radeon_connector->ddc_bus->has_aux) {
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if (radeon_connector->ddc_bus && radeon_connector->ddc_bus->has_aux) {
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drm_dp_aux_unregister(&radeon_connector->ddc_bus->aux);
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radeon_connector->ddc_bus->has_aux = false;
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}
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@ -104,6 +104,14 @@ static const char radeon_family_name[][16] = {
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"LAST",
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};
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#if defined(CONFIG_VGA_SWITCHEROO)
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bool radeon_has_atpx_dgpu_power_cntl(void);
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bool radeon_is_atpx_hybrid(void);
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#else
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static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
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static inline bool radeon_is_atpx_hybrid(void) { return false; }
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#endif
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#define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
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#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
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if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
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rdev->flags &= ~RADEON_IS_PX;
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/* disable PX is the system doesn't support dGPU power control or hybrid gfx */
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if (!radeon_is_atpx_hybrid() &&
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!radeon_has_atpx_dgpu_power_cntl())
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rdev->flags &= ~RADEON_IS_PX;
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}
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/**
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