dmaengine: at_hdmac: platform data move to use .id_table
We remove the use of platform data from DMA controller driver. We now use of .id_table to distinguish between compatible types. The two implementations allow to determine the number of channels and the capabilities of the controller. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>hifive-unleashed-5.1
Nicolas Ferre
Vinod Koul
parent
1ea6b8f489
commit
67348450b8
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@ -1175,6 +1175,18 @@ static void atc_free_chan_resources(struct dma_chan *chan)
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/*-- Module Management -----------------------------------------------*/
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static struct platform_device_id atdma_devtypes[] = {
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{
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.name = "at91sam9rl_dma",
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.driver_data = ATDMA_DEVTYPE_SAM9RL,
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}, {
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.name = "at91sam9g45_dma",
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.driver_data = ATDMA_DEVTYPE_SAM9G45,
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}, {
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/* sentinel */
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}
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};
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/**
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* at_dma_off - disable DMA controller
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* @atdma: the Atmel HDAMC device
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@ -1193,18 +1205,32 @@ static void at_dma_off(struct at_dma *atdma)
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static int __init at_dma_probe(struct platform_device *pdev)
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{
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struct at_dma_platform_data *pdata;
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struct resource *io;
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struct at_dma *atdma;
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size_t size;
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int irq;
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int err;
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int i;
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u32 nr_channels;
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dma_cap_mask_t cap_mask = {};
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enum atdma_devtype atdmatype;
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/* get DMA Controller parameters from platform */
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pdata = pdev->dev.platform_data;
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if (!pdata || pdata->nr_channels > AT_DMA_MAX_NR_CHANNELS)
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dma_cap_set(DMA_MEMCPY, cap_mask);
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/* get DMA parameters from controller type */
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atdmatype = platform_get_device_id(pdev)->driver_data;
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switch (atdmatype) {
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case ATDMA_DEVTYPE_SAM9RL:
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nr_channels = 2;
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break;
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case ATDMA_DEVTYPE_SAM9G45:
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nr_channels = 8;
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dma_cap_set(DMA_SLAVE, cap_mask);
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break;
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default:
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return -EINVAL;
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}
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io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!io)
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@ -1215,14 +1241,15 @@ static int __init at_dma_probe(struct platform_device *pdev)
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return irq;
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size = sizeof(struct at_dma);
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size += pdata->nr_channels * sizeof(struct at_dma_chan);
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size += nr_channels * sizeof(struct at_dma_chan);
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atdma = kzalloc(size, GFP_KERNEL);
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if (!atdma)
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return -ENOMEM;
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/* discover transaction capabilites from the platform data */
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atdma->dma_common.cap_mask = pdata->cap_mask;
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atdma->all_chan_mask = (1 << pdata->nr_channels) - 1;
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/* discover transaction capabilities */
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atdma->dma_common.cap_mask = cap_mask;
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atdma->all_chan_mask = (1 << nr_channels) - 1;
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atdma->devtype = atdmatype;
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size = resource_size(io);
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if (!request_mem_region(io->start, size, pdev->dev.driver->name)) {
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@ -1268,7 +1295,7 @@ static int __init at_dma_probe(struct platform_device *pdev)
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/* initialize channels related values */
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INIT_LIST_HEAD(&atdma->dma_common.channels);
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for (i = 0; i < pdata->nr_channels; i++) {
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for (i = 0; i < nr_channels; i++) {
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struct at_dma_chan *atchan = &atdma->chan[i];
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atchan->chan_common.device = &atdma->dma_common;
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@ -1313,7 +1340,7 @@ static int __init at_dma_probe(struct platform_device *pdev)
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dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n",
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dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "",
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dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",
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pdata->nr_channels);
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nr_channels);
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dma_async_device_register(&atdma->dma_common);
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@ -1495,6 +1522,7 @@ static const struct dev_pm_ops at_dma_dev_pm_ops = {
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static struct platform_driver at_dma_driver = {
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.remove = __exit_p(at_dma_remove),
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.shutdown = at_dma_shutdown,
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.id_table = atdma_devtypes,
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.driver = {
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.name = "at_hdmac",
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.pm = &at_dma_dev_pm_ops,
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@ -248,9 +248,16 @@ static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
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/*-- Controller ------------------------------------------------------*/
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enum atdma_devtype {
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ATDMA_DEVTYPE_UNDEFINED = 0,
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ATDMA_DEVTYPE_SAM9RL, /* compatible with SAM9RL DMA controller */
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ATDMA_DEVTYPE_SAM9G45, /* compatible with SAM9G45 DMA controller */
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};
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/**
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* struct at_dma - internal representation of an Atmel HDMA Controller
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* @chan_common: common dmaengine dma_device object members
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* @atdma_devtype: identifier of DMA controller compatibility
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* @ch_regs: memory mapped register base
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* @clk: dma controller clock
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* @save_imr: interrupt mask register that is saved on suspend/resume cycle
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@ -260,6 +267,7 @@ static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
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*/
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struct at_dma {
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struct dma_device dma_common;
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enum atdma_devtype devtype;
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void __iomem *regs;
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struct clk *clk;
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u32 save_imr;
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