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net: stmmac: add EHL PSE0 & PSE1 1Gbps PCI info and PCI ID 

Add EHL PSE0/1 RGMII & SGMII 1Gbps PCI info and PCI ID

Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
alistair/sensors
Voon Weifeng 2020-03-31 01:05:11 +08:00 committed by David S. Miller
parent 58da0cfa6c
commit 67c08ac414
1 changed files with 75 additions and 0 deletions
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75
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
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@ -210,6 +210,66 @@ static struct stmmac_pci_info ehl_rgmii1g_pci_info = {
.setup = ehl_rgmii_data,
};
static int ehl_pse0_common_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
plat->bus_id = 2;
plat->phy_addr = 1;
return ehl_common_data(pdev, plat);
}
static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
return ehl_pse0_common_data(pdev, plat);
}
static struct stmmac_pci_info ehl_pse0_rgmii1g_pci_info = {
.setup = ehl_pse0_rgmii1g_data,
};
static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
return ehl_pse0_common_data(pdev, plat);
}
static struct stmmac_pci_info ehl_pse0_sgmii1g_pci_info = {
.setup = ehl_pse0_sgmii1g_data,
};
static int ehl_pse1_common_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
plat->bus_id = 3;
plat->phy_addr = 1;
return ehl_common_data(pdev, plat);
}
static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
return ehl_pse1_common_data(pdev, plat);
}
static struct stmmac_pci_info ehl_pse1_rgmii1g_pci_info = {
.setup = ehl_pse1_rgmii1g_data,
};
static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
return ehl_pse1_common_data(pdev, plat);
}
static struct stmmac_pci_info ehl_pse1_sgmii1g_pci_info = {
.setup = ehl_pse1_sgmii1g_data,
};
static int tgl_common_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
@ -480,12 +540,27 @@ static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
#define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937
#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30
#define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31
/* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
* which are named PSE0 and PSE1
*/
#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0
#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1
#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0
#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1
#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac
static const struct pci_device_id intel_eth_pci_id_table[] = {
{ PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_pci_info) },
{ PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_pci_info) },
{ PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_pci_info) },
{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID,
&ehl_pse0_rgmii1g_pci_info) },
{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID,
&ehl_pse0_sgmii1g_pci_info) },
{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID,
&ehl_pse1_rgmii1g_pci_info) },
{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID,
&ehl_pse1_sgmii1g_pci_info) },
{ PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_pci_info) },
{}
};